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Encyclopedia of Algorithms pp 143–146Cite as

Circuit Placement

2000; Caldwell, Kahng, Markov 2002; Kennings, Markov 2006; Kennings, Vorwerk

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Keywords and Synonyms

EDA ; Netlist ; Layout ; Min-cut placement ; Min-cost max-flow ; Analytical placement; Mathematical programming                        

Problem Definition

This problem is concerned with efficiently determining constrained positions of objects while minimizing a measure of interconnect between the objects, as in physical layout of integrated circuits, commonly done in 2‐dimensions. While most formulations are NP-hard, modern circuits are so large that practical algorithms for placement must have near-linear runtime and memory requirements, but not necessarily produce optimal solutions. While early software for circuit placement was based on Simulated Annealing, research in algorithms identified more scalable techniques which are now being adopted in the Electronic Design Automation industry.

One models a circuit by a hypergraph G h (V h ,E h ) with (i) vertices \( V_h=\{v_1,\ldots,v_n\} \) representing logic gates, standard cells, larger modules, or fixed I/O pads and (ii) hyperedges \(...

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Recommended Reading

  1. Alpert, C.J., Chan, T., Kahng, A.B., Markov, I.L., Mulet, P.: Faster minimization of linear wirelength for global placement. IEEE Trans. CAD 17(1), 3–13 (1998)

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  2. Caldwell, A.E., Kahng, A.B., Markov, I.L.: Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. CAD 19(11), 1304–1314 (2000)

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  3. Chan, T., Cong, J., Sze, K.: Multilevel generalized force-directed method for circuit placement. Proc. Intl. Symp. Physical Design. ACM Press, San Francisco, 3–5 Apr 2005. pp. 185–192 (2005)

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  4. Ausiello, G., Crescenzi, P., Gambosi, G., Kann, V., Marchetti-Spaccamela, A., Protasi, M.: Complexity and Approximation: Combinatorial optimization problems and their approximability properties. Springer (1998)

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  5. Hu, B., Marek-Sadowska, M.: Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. CAD 24(8), 1188–1203 (2005)

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  6. Kahng, A.B., Wang, Q.: Implementation and extensibility of an analytic placer. IEEE Trans. CAD 24(5), 734–747 (2005)

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  7. Kennings, A., Markov, I.L.: Smoothing max-terms and analytical minimization of half‐perimeter wirelength. VLSI Design 14(3), 229–237 (2002)

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  8. Kennings, A., Vorwerk, K.: Force-directed methods for generic placement. IEEE Trans. CAD 25(10), 2076–2087 (2006)

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  9. Papa, D.A., Markov, I.L.: Hypergraph partitioning and clustering. In: Gonzalez, T. (ed.) Handbook of algorithms. Taylor & Francis Group, Boca Raton, CRC Press, pp. 61–1 (2007)

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  10. Reda, S., Chowdhary, A.: Effective linear programming based placement methods. In: ACM Press, San Jose, 9–12 Apr 2006

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  11. Roy, J.A., Adya, S.N., Papa, D.A., Markov, I.L.: Min-cut floorplacement. IEEE Trans. CAD 25(7), 1313–1326 (2006)

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  12. Tang, X., Tian, R., Wong, M.D.F.: Optimal redistribution of white space for wirelength minimization. In: Tang, T.-A. (ed.) Proc. Asia South Pac. Design Autom. Conf., ACM Press, 18–21 Jan 2005, Shanghai. pp. 412–417 (2005)

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Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada

    Andrew A. Kennings

  2. Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA

    Igor L. Markov

Authors
  1. Andrew A. Kennings
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  2. Igor L. Markov
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Editor information

Editors and Affiliations

  1. Department of Electrical Engineering and Computer ScienceMcCormick School of Engineering and Applied Science, Northwestern University, Evanston, IL, 60208, USA

    Ming-Yang Kao Professor of Computer Science

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© 2008 Springer-Verlag

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Kennings, A., Markov, I. (2008). Circuit Placement. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-30162-4_69

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