Abstract
Arithmetic Bit-Level (ABL) normalization has been proven a viable approach to formal property checking of datapath designs. It is applicable where arithmetic bit level components and sub-components can be identified at the register-transfer (RT) level of the design and the property. This chapter extends the applicability of ABL normalization to cases where some of the arithmetic components are custom-designed entities, e.g., specified using Boolean equations or gates. We transform these entities into ABL building blocks using Reed–Muller expressions as an intermediate representation. We show how Boolean logic expressed in Reed–Muller form can be automatically transformed into ABL components so that such logic blocks can be treated together with the remaining ABL components in a subsequent normalization run. The approach is evaluated on a number of industrial designs generated by a commercial arithmetic module generator.
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References
G. Audemard, P. Bertoli, A. Cimatti, A. Kornilowicz, and R. Sebastiani. A SAT-based approach for solving formulas over boolean and linear mathematical propositions. In Proc. International Conference on Automated Deduction (CAD), pages 195–210, 2002.
Boolector. http://fmv.jku.at/boolector.
R.E. Bryant and Y.-A. Chen. Verification of arithmetic circuits with binary moment diagrams. In DAC ’95: Proceedings of the 32nd ACM/IEEE Conference on Design Automation, pages 535–541. Assoc. Comput. Mach., New York, 1995.
D. Chai and A. Kuehlmann. A fast pseudo-boolean constraint solver. In Proc. International Design Automation Conference (DAC), pages 830–835, 2003.
M. Ciesielski, Z. Zeng, P. Kalla, and B. Rouzeyre. Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification. In Proc. International Conference on Design, Automation and Test in Europe (DATE), pages 285–291, 2002.
R. Drechsler, B. Becker, A. Sarabi, M. Theobald, and M. Perkowski. Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams. In Proc. International Design Automation Conference (DAC), pages 415–419, 1994.
H. Ganzinger, G. Hagen, R. Nieuwenhuis, A. Oliveras, and C. Tinelli. DPLL(T): Fast decision procedures. In Proc. International Conference on Computer Aided Verification (CAV), pages 26–37, July 2004.
K. Hamaguchi, A. Morita, and S. Yajima. Efficient construction of binary moment diagrams for verifying arithmetic circuits. In Proc. International Conference on Computer-Aided Design (ICCAD), pages 78–82, November 1995.
U. Kebschull, E. Schubert, and W. Rostenstiel. Multi-level logic based on functional decision diagrams. In Proc. European Design Automation Conference (EDAC), pages 43–47, 1992.
U. Krautz, C. Jacobi, K. Weber, M. Pflanz, W. Kunz, and M. Wedler. Verifying full-custom multipliers by boolean equivalence checking and an arithmetic bit level proof. In ASP-DAC ’08: Proceedings of the 2008 Conference on Asia and South Pacific Design Automation, pages 398–403. IEEE Comput. Soc., Los Alamitos, 2008.
Onespin Solutions GmbH, Germany. OneSpin 360MV. www.onespin-solutions.com.
N. Shekhar, P. Kalla, and F. Enescu. Equivalence verification of polynomial datapaths using ideal membership testing. IEEE Transactions on Computer-Aided Design, 26(7):1320–1330, 2007.
Spear. http://www.domagoj-babic.com.
D. Stoffel and W. Kunz. Equivalence checking of arithmetic circuits on the arithmetic bit level. IEEE Transactions on Computer-Aided Design, 23(5):586–597, 2004.
S. Vasudevan, V. Viswanath, R.W. Sumners, and J.A. Abraham. Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems. IEEE Transactions on Computers, 56(10):1401–1414, 2007.
Y. Watanabe, N. Homma, T. Aoki, and T. Higuchi. Application of symbolic computer algebra to arithmetic circuit verification. In Proc. International Conference on Computer Design (ICCD), pages 25–32, October 2007.
M. Wedler, D. Stoffel, R. Brinkmann, and W. Kunz. A normalization method for arithmetic data-path verification. IEEE Transactions on Computer-Aided Design, 26(11):1909–1922, 2007.
S. Wefel and P. Molitor. Prove that a faulty multiplier is faulty!? In GLSVLSI ’00: Proceedings of the 10th Great Lakes symposium on VLSI, pages 43–46. Assoc. Comput. Mach., New York, 2000.
O. Wienand, M. Wedler, G.-M. Greuel, D. Stoffel, and W. Kunz. An algebraic approach for proving data correctness in arithmetic data paths. In Proc. International Conference Computer Aided Verification (CAV), pages 473–486. Princeton, NJ, USA, July 2008.
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Pavlenko, E., Wedler, M., Stoffel, D., Kunz, W., Wienand, O., Karibaev, E. (2009). A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level. In: Radetzki, M. (eds) Languages for Embedded Systems and their Applications. Lecture Notes in Electrical Engineering, vol 36. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9714-0_17
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