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Adaptive Data Compression for Low-Power On-Chip Networks

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Low Power Networks-on-Chip

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Abstract

With the recent design shift toward increasing the number of processing elements in a chip, supports for low power, low latency, and high bandwidth in on-chip interconnect are essential. Much of the previous work has focused on router architectures and network topologies using wide/long channels. However, such solutions may result in a complicated router design and a high interconnect power/area cost. In this chapter, we present a method to exploit a table-based data compression technique, relying on value patterns in cache traffic. Compressing a large packet into a small one saves power consumption by reducing required operations in network components and decreases contention by increasing the effective bandwidth of shared resources. The main challenges are providing a scalable implementation of tables and minimizing the latency overhead of compression. We propose a shared table scheme that needs one encoding and one decoding tables for each processing element, and a management protocol that does not require in-order delivery. This scheme eliminates table size dependence on a network size, which realizes scalability and reduces overhead cost of table for compression. Our simulation results are presented for 8-core and 16-core designs. Overall, our compression method improves the packet latency up to 44% with an average of 36% and reduces the network power consumption by 36% on average in 16-core tiled design.

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Notes

  1. 1.

    A flow represents a pair of source and destination. Therefore, an n-node network has n 2 flows.

  2. 2.

    Most routers have eight ports. Additionally, 12 routers have nine ports to connect a core (eight routers at periphery) or a memory controller (four routers in the center).

  3. 3.

    A flit can be subdivided into multiple physical transfer units (phits). Each phit is transferred across a channel in a single cycle. We assume that the phit size is equal to the flit size in this chapter.

  4. 4.

    VC allocator (R → p) has the longest latency among others and determines the delay of a router pipeline in both designs. Therefore, the number of VCs is selected for one clock cycle time.

  5. 5.

    We put the value table at the router rather than each node in SNUCA-CMP.

  6. 6.

    The destination sharing degree (dest) is the average number of destinations for each value. The source sharing degree (src) is the average number of sources for each value.

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Acknowledgements

This work was supported in part by NSF grants CCF-0541360 and CCF-0541384. Yuho Jin is currently supported by the National Science Foundation under Grant no. 0937060 to the Computing Research Association for the CIFellows Project.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Southern California, 3740 McClintock Ave., Los Angeles, CA, 90089, USA

    Yuho Jin

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  1. Yuho Jin
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  2. Ki Hwan Yum
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  3. Eun Jung Kim
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Correspondence to Yuho Jin .

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  1. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Cristina Silvano

  2. NEC Laboratories America, Inc., Independence Way 4, Princeton, 08540, New Jersey, USA

    Marcello Lajolo

  3. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Gianluca Palermo

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Jin, Y., Yum, K.H., Kim, E.J. (2011). Adaptive Data Compression for Low-Power On-Chip Networks. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_6

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  • DOI: https://doi.org/10.1007/978-1-4419-6911-8_6

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