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Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges

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Abstract

This chapter provides a brief overview of the principles and challenges of ultra-low power circuit design in the subthreshold region of operation. Design principles at all levels of hierarchy, namely, devices, circuits, and architecture need to be evaluated for maximum power gains. Brief description of SRAM design techniques as well as alternative architectures for lower power has also been discussed.

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Acknowledgments

The authors would like to acknowledge the contributions and helpful discussions with Prof Kaushik Roy, Mr. Sumeet Gupta, Mr. M. Hwang, and other members of the Nanoelectronics Research Lab in Purdue University.

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Authors and Affiliations

  1. Global Foundries, Fishkill, NY, USA

    Bipul C. Paul

  2. Intel Corporation, Portland, OR, USA

    Arijit Raychowdhury

Authors
  1. Bipul C. Paul
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  2. Arijit Raychowdhury
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Correspondence to Bipul C. Paul .

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Editors and Affiliations

  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

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Paul, B.C., Raychowdhury, A. (2011). Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_6

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  • DOI: https://doi.org/10.1007/978-1-4419-7418-1_6

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-7417-4

  • Online ISBN: 978-1-4419-7418-1

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