Abstract
In this chapter, we focus on 3-D Network-on-Chip (NoC) architecture that uses a wireless inductive coupling for vertical interconnection. Because chips are wirelessly connected, the addition, removal, and swapping of known-good-dies in a package are possible after fabrication. We introduce a 3-D NoC architecture that can exploit this flexibility. Then, we introduce a 3-D dynamically reconfigurable processors called MuCCRA-Cube, as an implementation example of the wireless 3-D architecture.
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- 1.
A tier refers to a die in a 3-D IC.
- 2.
A pillar refers to a vertical connection between the service and application chips, via a vertical crossbar and corresponding TX/RX modules (Fig. 10.3d).
References
H. Amano and Y. Hasegawa and S. Tsutsumi and T. Nakamura and T. Nishimura and V. Tanbunheng and A. Parimala and T. Sano and M. Kato. MuCCRA Chips: Configurable Dynamically-Reconfigurable Processors. Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC’07), pages 384–387, 2007.
B. Black and M. Annavaram and N. Brekelbaum and J. DeVale and L. Jiang and G. H. Loh and D. McCaule and P. Morrow and D. W. Nelson and D. Pantuso and P. Reed and J. Rupley and S. Shankar and J. P. Shen and C. Webb. Die Stacking (3D) Microarchitecture. Proceedings of the International Symposium on Microarchitecture (MICRO’06), pages 469–479, 2006.
J. Burns and L. McIlrath and C. Keast and C. Lewis and A. Loomis and K. Warner and P. Wyatt. Three-Dimensional Integrated Circuits for Low-Power High-Bandwidth Systems on a Chip. Proceedings of the International Solid-State Circuits Conference (ISSCC’01), pages 268–269, 2001.
W. R. Davis and J. Wilson and S. Mick and J. Xu and H. Hua and C. Mineo and A. M. Sule and M. Steer and P. D. Franzon. Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design and Test of Computers, 22(6):498–510, 2005.
A. Fazzi and L. Magagmni and M. Mirandola and B. Charlet and L. D. Cioccio and E. Jung and R. Canegallo and R. Guerrieri. 3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly. IEEE Journal of Solid-State Circuits, 42(10):2270–2282, 2007.
K. Kanda and D. D. Antono and K. Ishida and H. Kawaguchi and T. Kuroda and T. Sakurai. 1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme. Proceedings of the International Solid-State Circuits Conference (ISSCC’03), pages 186–187, 2003.
J. Kim and C. Nicopoulos and D. Park and R. Das and Y. Xie and N. Vijaykrishnan and M. Yousif and C. Das. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Proceedings of the International Symposium on Computer Architecture (ISCA’07), pages 138–149, 2007.
K. Kumagai and C. Yang and S. Goto and T. Ikenaga and Y. Mabuchi and K. Yoshida. System-in-Silicon Architecture and its Application to an H.264/AVC Motion Estimation fort 1080HDTV. Proceedings of the International Solid-State Circuits Conference (ISSCC’06), pages 430–431, 2006.
F. Li and C. Nicopoulos and T. Richardson and Y. Xie and V. Narayanan and M. Kandemir. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. Proceedings of the International Symposium on Computer Architecture (ISCA’06), pages 130–141, 2006.
H. Matsutani and M. Koibuchi and H. Amano. Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. Proceedings of the International Conference on Parallel Processing (ICPP’07), 2007.
M. Miura and H. Ishikuro and K. Niitsu and T. Sakurai and T. Kuroda. A 0.14 pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping. IEEE Journal of Solid-State Circuits, 43(1):285–291, 2008.
N. Miura and D. Mizoguchi and M. Inoue and K. Niitsu and Y. Nakagawa and M. Tago and M. Fukaishi and T. Sakurai and T. Kuroda. A 1Tb/s 3 W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link. Proceedings of the International Solid-State Circuits Conference (ISSCC’06), pages 424–425, 2006.
N. Miura and H. Ishikuro and T. Sakurai and T. Kuroda. A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. Proceedings of the International Solid-State Circuits Conference (ISSCC’07), pages 358–359, 2007.
D. Park and S. Eachempati and R. Das and A. K. Mishra and V. Narayanan and Y. Xie and C. R. Das. MIRA: A Multi-layered On-Chip Interconnect Router Architecture. Proceedings of the International Symposium on Computer Architecture (ISCA’08), pages 251–261, 2008.
V. F. Pavlidis and E. G. Friedman. 3-D Topologies for Networks-on-Chip. IEEE Transactions on Very Large Scale Integration Systems, 15(10):1081–1090, 2007.
R. S. Ramanujam and B. Lin. Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks. IEEE Computer Architecture Letters, 7(2):37–40, 2008.
V. Tunbunheng and H. Amano. DisCounT: Disable Configuration Technique for Representing Register and Reducing Configuration Bits in Dynamically Reconfigurable Architecture. Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI’07), pages 412–419, 2007.
V. Tunbunheng and M. Suzuki and H. Amano. RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. Proceedings of the International Conference on Field Programmable Technology (ICFPT’05), pages 129–136, 2005.
Y. Yuan and Y. Yoshida and N. Yamaguchi and T. Kuroda. Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme. Japanese Journal of Applied-Physics, 47(4):2797–2800, 2008.
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Matsutani, H., Koibuchi, M., Kuroda, T., Amano, H. (2011). 3-D NoC on Inductive Wireless Interconnect. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_10
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