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Physical Analysis of NoC Topologies for 3-D Integrated Systems

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Book cover 3D Integration for NoC-based SoC Architectures

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

The manufacturing of integrated systems in multiple physical planes provides new opportunities for on-chip interconnection networks. Topologies of networks on-chip that have been of limited use due to the long and, therefore, slower interconnects can now be efficiently implemented in a vertically integrated circuit. Three-dimensional meshes are, reasonably, the first to be explored due to the simplicity of these topologies. Considerable improvements in delay and power can result from these topologies. These improvements originate either from the shorter interconnects or the decrease in the number of switches that data packets traverse to reach the destination network node. To evaluate the benefits obtained by a 3-D mesh on-chip network, appropriate latency and power models are described in this chapter. The accurate evaluation of the performance of these networks should be augmented by temperature-aware models that incorporate the power consumed by the processing elements of the network in addition to the power of the network links and switches. A methodology that includes these models is employed to determine the interconnect architecture within the PEs in each physical plane of a 3-D on-chip network.

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Author information

Authors and Affiliations

  1. Integrated Systems Laboratory, EPFL, 1015, Lausanne, Switzerland

    Vasilis F. Pavlidis

  2. University of Rochester, 14627, Rochester, NY, USA

    Eby G. Friedman

Authors
  1. Vasilis F. Pavlidis
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  2. Eby G. Friedman
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Corresponding authors

Correspondence to Vasilis F. Pavlidis or Eby G. Friedman .

Editor information

Editors and Affiliations

  1. TIMA Laboratory, 46, Avenue Felix Viallet, Grenoble, 38000, France

    Abbas Sheibanyrad

  2. TIMA Laboratory, Avenue Felix Viallet 46, Grenoble, 38000, France

    Frédéric Pétrot

  3. Royal Institute of Technology, Forum 120, Kista, SE-16440, Sweden

    Axel Jantsch

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Pavlidis, V.F., Friedman, E.G. (2011). Physical Analysis of NoC Topologies for 3-D Integrated Systems. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_5

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  • DOI: https://doi.org/10.1007/978-1-4419-7618-5_5

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  • Online ISBN: 978-1-4419-7618-5

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