Abstract
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging Systems-on-Chip (SoC) design paradigms based on Networks-on-Chip (NoC) interconnection architectures to 3D chip designs. In this chapter, we consider the problem of designing application-specific 3D-NoC architectures that are optimized for a given application. Both unicast and multicast traffic flows are supported. We present novel 3D-NoC synthesis algorithms that make use of accurate power and delay models for 3D wiring with through-silicon vias. In particular, we present a very efficient 3D-NoC synthesis algorithm called Ripup-Reroute-and-Router-Merging (RRRM), that is based on a rip-up and reroute formulation for routing flows and a router merging procedure for network optimization. Experimental results on 3D-NoC design cases show that our synthesis results can on average achieve significant improvements over regular mesh-based 3D implementations, both in terms of power consumption as well as hop counts.
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- 1.
Since inserting TSV adds delay, we tighten the delay constraints by some extent to get valid solutions.
- 2.
In the experiments, we’ve tried several flow ordering strategies such as largest flow first, smallest flow first, random ordering et al., and we found the ordering of smallest flow first gave the best results. Thus we used this ordering in our experiments. Also, we observed that repeating the whole RIPUP-REROUTE procedure twice is enough to generate good results.
- 3.
This extended channel dependency graph construction treats unicast flows as a special case.
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Yan, S., Lin, B. (2011). Design of Application-Specific 3D Networks-on-Chip Architectures. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_8
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