Abstract
Nanotechnology research is an enabling field and is closely aligned with advances in neuromorphic architectures, energy efficient computing, and autonomy efforts. The development of neuromorphic circuits leverages a mixture of proven CMOS technologies with experimental devices and architectures that pose significant challenges for integration and fabrication. This chapter examines the pressures pushing the development of unconventional computing designs for size, weight, and power constrained environments and briefly reviews some of the trends that are influencing the development of solid-state neuromorphic systems. Later sections provide high level examples of selected approaches to hardware design and fabrication.
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Wysocki, B., McDonald, N., Thiem, C., Rose, G., Gomez, M. (2014). Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments. In: Pino, R. (eds) Network Science and Cybersecurity. Advances in Information Security, vol 55. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7597-2_9
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DOI: https://doi.org/10.1007/978-1-4614-7597-2_9
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