Years and Authors of Summarized Original Work
1993; Rajaraman, Wong
Problem Definition
Circuit partitioning consists of dividing the circuit into parts, each of which can be implemented as a separate component (e.g., a chip) that satisfies the design constraints. The work of Rajaraman and Wong [5] considers the problem of dividing a circuit into components, subject to area constraints, such that the maximum delay at the outputs is minimized.
A combinational circuit can be represented as a directed acyclic graph G = (V, E), where V is the set of nodes and E is the set of directed edges. Each node represents a gate in the network and each edge (u, v) in E represents an interconnection between gates u and v in the network. The fanin of a node is the number of edges incident into it, and the fanout of a node is the number of edges incident out of it. A primary input (PI) is a node with fanin 0, while a primary output (PO) is a node with fanout 0. Each node has a weight and a delay...
Keywords
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsRecommended Reading
Cong J, Ding Y (1992) An optimal technology mapping algorithm for delay optimization in lookup-table based fpga design. In: Proceedings of IEEE international conference on computer-aided design, Santa Clara, pp 48–53
Lawler EL, Levitt KN, Turner J (1966) Module clustering to minimize delay in digital networks. IEEE Trans Comput C-18:47–57
Murgai R, Brayton RK, Sangiovanni-Vincentelli A (1991) On clustering for minimum delay/area. In: Proceedings of IEEE international conference on computer-aided design, Santa Clara, pp 6–9
Pan P, Karandikar AK, Liu CL (1998) Optimal clock period clustering for sequential circuits with retiming. IEEE Trans Comput-Aided Des Integr Circuits Syst 17:489–498
Rajaraman R, Wong DF (1995) Optimum clustering for delay minimization. IEEE Trans Comput-Aided Des Integr Circ Syst 14:1490–1495
Yang HH, Wong DF (1997) Circuit clustering for delay minimization under area and pinconstraints. IEEE Trans Comput-Aided Des Integr Circ Syst 16:976–986
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media New York
About this entry
Cite this entry
Rajaraman, R. (2016). Performance-Driven Clustering. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_291
Download citation
DOI: https://doi.org/10.1007/978-1-4939-2864-4_291
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4939-2863-7
Online ISBN: 978-1-4939-2864-4
eBook Packages: Computer ScienceReference Module Computer Science and Engineering