1 Introduction

Radio Frequency Identification (RFID) technology, as one of the key technologies of Internet of Things (IOTs), can identify objects by wireless communication. With the advantages of long communication range, high speed, multi objects identification and low cost, ultra-high frequency (UHF) RFID system has been wildly applied to systems of IOTs, such as logistics, traffic, anti-counterfeiting and trace [1,2,3].

The EPC Class-1 Generation-2 (Gen2) [4], which features high data-rate, large storage capacity, long operating range and moderate security, is the most popular UHF RFID standard, and has been absorbed as ISO/IEC 18000-6C by ISO. Many researches have been conducted to improve the performance of EPC Gen2 tags [4], and low power is often the first priority [5, 6]. However, the accuracy of backscatter link frequency (BLF) also plays an important role in tag design, because the reader cannot identify tags when the BLF of tags exceeds the frequency tolerance (FT) defined by EPC Gen2. Techniques proposed in [7, 8] obtain BLF by generating accurate clock frequency, which increase the design complexity of clock generator. BLF generation method by dividing the clock frequency is developed in [9], which uses (N + 0.5) divide ratio to reduce the BLF error. Unfortunately, when (N + 0.5) is less than 5.5, the duty-cycle of backscatter link data will larger than 55%, which exceeds the required range of 45%–55% by EPC Gen2.

In this paper, a novel BLF generation scheme is developed. By analyzing the effects of division ratio and division error on the accuracy of BLF, a BLF generation scheme with large clock variation-tolerance is proposed, which not only meets the required BLF accuracy of EPC Gen2, but also simplifies the design complexity of clock generator.

2 Brief Review of EPC Gen2 Standard

In EPC Gen2 standard, the reader utilizes a Pulse Interval Encoding (PIE) format to communicate with the tag. Figure 1(a) shows the PIE format. The length of data-0 symbol is one Tari while that of data-1 ranges from between 1.5Tari and 2Tari, and it is determined by the reader. Here, Tari is the timing reference with typical values of 6.25 µs, 12.5 µs and 25 µs.

Fig. 1.
figure 1

Symbols defined in EPC Gen2 standard: (a) PIE; (b) preamble.

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In EPC Gen2 standard, an inventory round is initiated by the Query command. The Query command is preceded by the preamble as shown in Fig. 1(b), in which RTcal and TRcal are reader-to-tag (R => T) calibration symbol and tag-to-reader (T => R) calibration symbol, respectively. The length of RTcal is the sum of data-0 symbol and data-1 symbol, and it is used to distinguish data-0 and data-1. When the symbol length is less than RTcal/2, it is interpreted as data-0, otherwise it is interpreted as data-1. The BLF is specified by TRcal symbol and the parameter DR in Query command. And BLF is defined as:

$$ BLF = \frac{DR}{TRcal} $$
(1)

where DR has two values: 8 or 64/3. The error of BLF should be within the frequency tolerance (FT) required by EPC Gen2 as shown in Table 1.

Table 1. FT of BLF in EPC GEN2
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3 BLF Generation Scheme

3.1 Error in BLF Generation

In digital domain, the length of TRcal is usually measured by counting the edges of clock. If the frequency of clock is fclk_sys, then the count number NTRcal of TRcal can be expressed as:

$$ N_{TRcal} = f_{clk\_sys} \times TRcal $$
(2)

Using Eqs. (1) and (2), the following equation can be arrived:

$$ \begin{aligned} BLF & = DR/(N_{TRcal} /f_{clk\_sys} ) \\ & = \frac{{f_{clk\_sys} }}{{(N_{TRcal} /DR)}} = \frac{{f_{clk\_sys} }}{Div} \\ \end{aligned} $$
(3)

where Div is the division ratio, and can be expressed as:

$$ Div = \frac{{N_{TRcal} }}{DR} $$
(4)

Usually, Div is obtained by right shift operation for low power consideration, then Eq. (4) can be rewritten as:

$$ \left\{ {\begin{array}{*{20}l} {R = \frac{{N_{TRcal} }}{64/3} = (3 \cdot N_{TRcal} ) > > 6,\,\,\,DR = 64/3} \hfill \\ {R = \frac{{N_{TRcal} }}{8} = N_{TRcal} > > 3, \,\,\,DR = 8} \hfill \\ \end{array} } \right. $$
(5)

where R is the integral part of Div. Unfortunately, large error can be introduced when using right shift operation to calculate Div. Figure 2 illustrates how the error E is introduced by right shift operation when DR = 8. It is clear that BLF error occurs when E ≠ 0. In [10], a fixed number is added to NTRcal when calculating Div to reduce the BLF error. However, it is assumed that the frequency of clock is 1.28 MHz, and the variation of clock due to process, voltage and temperature variations is not taken into consideration.

Fig. 2.
figure 2

Illustration of error due to right shift operation

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3.2 Relationship Between BLF Error and Division Ratio

As analyzed above, the error of BLF is caused by right shift operation shown in Fig. 2. Supposing the ideal BLF demanded by reader is BLFideal and the clock is fclk_sys, then Div can be expressed as:

$$ Div = \frac{{f_{clk\_sys} }}{{BLF_{ideal} }} $$
(6)

With rearrangement, we expressed Div as:

$$ Div = R + \sigma $$
(7)

where R is the integral part, σ is the fractional part. The proposed BLF generation scheme can be expressed as:

$$ \left\{ {\begin{array}{*{20}l} {R_{final} = R,\sigma < \sigma_{th} ;} \hfill \\ {R_{final} = R + 1,\sigma \ge \sigma_{th} ;} \hfill \\ \end{array} } \right. $$
(8)

Rfinal is the final division ratio for calculating BLF and σth is the threshold value for Rfinal calculation. Let error0 and error1 are the absolute errors of BLF corresponding to division ratio R and (R + 1), respectively. Using Eqs. (6) and (8), then BLFideal can be expressed as:

$$ BLF_{ideal} = \frac{{f_{clk\_sys} }}{R} - error0 $$
(9)
$$ BLF_{ideal} = \frac{{f_{clk\_sys} }}{R + 1} + error1 $$
(10)

As can be seen from Table 1, only the relative error of BLF is concerned. Thus, ε0 and ε1 are defined as the relative errors of BLF for R and (R + 1), respectively. And the following expressions can be obtained by using Eqs. (6–10):

$$ \varepsilon 0 = \frac{error0}{{BLF_{ideal} }} = \frac{\sigma }{R} $$
(11)
$$ \varepsilon 1 = \frac{error1}{{BLF_{ideal} }} = \frac{1 - \sigma }{R + 1} $$
(12)

The relationship between ε0, ε1 and σ under different R are evaluated and the simulation results are illustrated in Fig. 3. It can be observed that ε0 and ε1 decrease when R increases under a certain σ. If we choose σth equal to the value of σ when ε0 = ε1, then the maximum relative error εmax of BLF under a certain division ratio R can be obtained by the following equation:

Fig. 3.
figure 3

BLF error with different σ: (a) R = 2; (b) R = 3; (c) R = 5; (d) R = 6; (e) R = 10; (f) R = 20

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$$ \varepsilon_{\hbox{max} } = \varepsilon 0 = \frac{\sigma }{R} = \frac{1 - \sigma }{R + 1} = \varepsilon 1 $$
(13)

Solving the above equation, we can get:

$$ \sigma_{th} = \frac{R}{2R + 1} = 0.5 - \frac{0.5}{2R + 1} $$
(14)

If R is known, σth can be calculated by Eq. (14), and then εmax is obtained by Eq. (13). Thus, the BLF error ε can be expressed as:

$$ \left\{ {\begin{array}{*{20}c} {\varepsilon = \varepsilon 0,} & {\sigma < \sigma_{th} ;} \\ {\varepsilon = \varepsilon 1,} & {\sigma \ge \sigma_{th} ;} \\ \end{array} } \right. $$
(15)

In other words, the BLF error ε has the maximum error defined by Eq. (13) under a certain R.

According to Table 1, the maximum absolute error of BLF is 15% when BLF is 640 kHz. From Fig. 3, it can be seen that the minimum division ratio Rmin should be 3 to meet the FT requirement of BLF. As the maximum BLF is 640 kHz in EPC Gen2 standard, thus the minimum clock frequency for the proposed scheme is fclk_sys = BLFmax × Rmin × (1 − |FT|) = 640 kHz × 3 × (1 − 15%) = 1.632 MHz.

3.3 Proposed BLF Generation Scheme

From Eq. (14), it is clear that different R has different σth. If different R with its corresponding σth calculated by (14) is implemented, the design complexity is significantly increased. Fortunately, as can be seen from Eq. (13), BLF error reduces when R increases. Thus, if Rmin = 3 meets FT requirement of BLF shown in Table 1, then the implementation of the BLF generation scheme would be significantly simplified. Two cases are considered:

  1. (1)

    DR = 64/3

In this case, as Rmin = 3, the corresponding σth_ideal = 0.428. However, R is obtained by 6-bit right shift of (3∙NTRcal) as shown in Eq. (5). Thus, the actual σth_actual in digital circuit is:

$$ \sigma_{th\_actual} = \frac{{round(64 \times \sigma_{th\_ideal} )}}{64} = 0.422 $$
(16)

With σth = 0.422, the relationship between BLF error ε and division ratio R is simulated and the results is shown in Fig. 4. The maximum BLF error is 14.7% which is less than 15% required by EPC Gen2 standard.

Fig. 4.
figure 4

BLF error with σth = 0.422 when DR = 64/3

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  1. (2)

    DR = 8

As Table 1 listed, the maximum BLF is 465 kHz when DR = 8. The minimum clock frequency is 1.632 MHz as discussed above. Thus, the minimum Div is equal to 1.632 MHz/465 kHz = 3.51. Then the minimum value of R may equal to 3 or 4, and the corresponding σth_ideal is 0.428 or 0.444 by applying Eq. (14). Similar to the scenario of DR = 64/3, σth_ideal cannot be obtained because of the right shift operation. Thus, the acutal σth_actual of DR = 8 is:

$$ \sigma_{th\_actual} = \frac{{round(8 \times \sigma_{th\_ideal} )}}{8} = 0.375\,\text{or}\,0.5 $$
(17)

The simulation results are shown in Fig. 5. As calculated above, Div = 3.51 when BLF = 465 kHz and fclk_sys = 1.632 MHz, and the fractional part σ of Div is 0.51. Thus, Rfinal is 4 regardless of σth_actual = 0.375 or σth_actual = 0.5. From Fig. 5, it is clearly noted that BLF error of σth_actual = 0.5 is always less than that of σth_actual = 0.375 when R ≥ 4. So we choose σth = 0.5 when DR = 8.

Fig. 5.
figure 5

BLF error with different σth when DR = 8

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For FT inflection points of different BLF, the final division ratio Rfinal and BLF error at fclk_sys = 1.632 MHz is calculated and listed in Table 2. It can be seen that the accuracy of BLF meets the requirements of EPC Gen2 standard. For a certain BLF, when the clock frequency increases, the division ratio also increases, so the BLF error will never exceeds the maximum BLF error shown in Table 2 except BLF = 640 kHz. That is because when fclk_sys = 1.632 MHz and BLF = 640 kHz, the division ratio Div < 3, and the above simulation results are based on Div ≥ 3. However, the actual BLF will never exceeds FT of EPC Gen2 when fclk_sys ≥ 1.632 MHz.

Table 2. Maximum BLF error (fclk_sys = 1.632 MHz)
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4 Simulation Results

To validate the robustness of the proposed BLF generation scheme, we simulated the BLF error under different lengths of TRcal with different clock frequencies. Figure 6 shows the simulation results. It can be noted that the proposed BLF generation scheme can meet the FT requirement of EPC Gen2 in a large frequency range, which is an important improvement on tag design.

Fig. 6.
figure 6

Relationship of BLF error and TRcal over different clock frequencies: (a) DR = 64/3; (b) DR = 8.

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5 Conclusion

A novel BLF generation scheme for UHF RFID tag complying with EPC Gen2 standard is presented. By analyzing the effects of division ratio and division error on the accuracy of BLF, a BLF generation scheme with clock variance-tolerant is proposed. Simulation results show that the scheme can generate BLF satisfied the requirement of EPC Gen2 when the clock frequency is no less than 1.632 MHz, which significantly relaxes the accuracy of clock generator.