Abstract
Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and restructuring with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Languages (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a fully automated solution which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.
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Kalsing, A., Fesquet, L., Aktouf, C. (2019). A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. In: Große, D., Vinco, S., Patel, H. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 530. Springer, Cham. https://doi.org/10.1007/978-3-030-02215-0_6
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DOI: https://doi.org/10.1007/978-3-030-02215-0_6
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