Investigation of L2-Cache Interferences in a NXP QorIQ T4240 Multi-core Processor

Abstract

The CPU cache memory was invented to reduce access latency between the processor and the main memory. Instructions and data are fetched from a fast cache instead of a slow memory to save hundreds of cycles. But new kinds of cache interferences were introduced with the arise of multi-core technology.

Safety-critical systems and especially higher functional integrated systems in avionics require an assurance that interferences do not influence functionality to maintain certification capability. Furthermore, interferences caused by cache misses result in a decrease of the processors overall performance.

This paper focuses on the investigation of the L2 cache interferences of a modern commercial-of-the-shelf (COTS) PowerPC based processor as in to how and why they occur. The investigation regards to interferences caused by the multi-core design. In order to realise the problem, a comprehensive understanding of the underlying architecture and the principle function of cache is a necessary prerequisite.

A detailed analysis investigates vulnerabilities in the architecture before these are then exploited by the use of targeted memory arithmetic. A series of measurements performed by a simulation framework, reveals the extent to which these vulnerabilities can affect the runtime of applications.

The results clearly show that the design of a multi-core processor (SMT) not only brings benefits but also risks in terms of performance and runtime. Thus, interferences due to the multi-core design should be avoided if possible, especially given safety-critical guidelines.