Abstract
For FPGA applications in the application domains requiring a high degree of functional safety such as automotive and industrial infrastructure, simple homogeneous redundant logic design, where the same hardware modules are simply replicated, is not enough. In order to improve tolerance to common cause fault, heterogeneous redundant design, where different implementation approaches are taken for realizing the same logic functionality, is crucial. However, manual redundant design tends to place a burden on designers, reducing productivity of system development. To cope with this problem, this paper proposes a systematic heterogeneous redundant design approach for finite state machines on FPGAs, focusing on the diversity of state encoding methods. With this approach, designers can easily combine the state machines with different encoding to form heterogeneous redundancy, by inserting simple directives into RTL source code. In order to evaluate the effectiveness of the proposed approach, timing analysis of post-layout netlists is performed under an overclock situation as an example of common cause fault. The evaluation results demonstrate the proposed approach improves the error detection rate compared to conventional homogeneous redundant designs. It is also discussed how the choice of state encoding methods impacts the error detection rate.
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References
Hayek, A., Al-Bokhaiti, M., Borcsok, J.: Design and implementation of an FPGA-based 1oo4-architecture for safety-related system-on-chip. In: Proceedings IEEE 25th International Conference on Microelectronics (ICM), pp. 1–4 (2013)
Ichinomiya, Y., Tanoue, S., Ishida, T., Amagasaki, M., Kuga, M., Sueyoshi, T.: Memory sharing approach for TMR softcore processor. In: Reconfigurable Computing: Architectures, Tools and Applications, pp. 268–274. Springer (2009)
International Electrotechnical Commission: Functional safety of electrical/electronic/programmable electronic safety related systems. IEC 61508 (2000)
Konoura, H., Imagawa, T., Mitsuyama, Y., Hashimoto, M., Onoye, T.: Comparative evaluation of lifetime enhancement with fault avoidance on dynamically reconfigurable devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97(7), 1468–1482 (2014)
Lovric, T.: Systematic and design diversity — software techniques for hardware fault detection. In: Dependable Computing — EDCC-1, pp. 307–326. Springer (1994)
Morimoto, K., Shibata, Y., Shirakura, Y., Maruta, H., Tanaka, M., Kurokawa, F.: Diversity diagnostic for new FPGA based controller of renewable energy power plant. Int. J. Renew. Energy Res. 7, 1403–1412 (2017)
Shirakura, Y., Segawa, T., Shibata, Y., Morimoto, K., Tanaka, M., Nobe, M., Maruta, H., Kurokawa, F.: A redundant design approach with diversity of FPGA resource mapping. In: Proceedings of International Symposium on Applied Reconfigurable Computing (ARC 2016). Lecture Notes in Computer Science, vol. 9625, pp. 119–131 (2016)
Yang, S.: Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 (1991)
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Itagawa, T., Kamasaka, R., Shibata, Y. (2020). A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs. In: Barolli, L., Hussain, F., Ikeda, M. (eds) Complex, Intelligent, and Software Intensive Systems. CISIS 2019. Advances in Intelligent Systems and Computing, vol 993. Springer, Cham. https://doi.org/10.1007/978-3-030-22354-0_40
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DOI: https://doi.org/10.1007/978-3-030-22354-0_40
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