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Two FPGA Devices in the Problem of Finding Minimal Reducts

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Computer Information Systems and Industrial Management (CISIM 2019)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 11703))

Abstract

Speeding up attribute reduction process is an important issue in data mining. The goal of this paper is to compare two hardware implementations of minimal reducts computation, i.e. the previously introduced implementation on Intel Arria V SoC and a newly proposed solution on Xilinx Zynq Ultrascale+ MPSoC. Two versions of an attribute reduction algorithm, i.e. blind and frequency based breadth search strategies, were implemented on the two frameworks. Experimental research showed that finding minimal reducts can be accelerated several times when using the new device.

This work was supported by the grant S/WI/1/2018 of the Polish Ministry of Science and Higher Education.

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References

  1. Chen, D., Zhao, S., Zhang, L., Yang, Y., Zhang, X.: Sample pair selection for attribute reduction with rough set. IEEE Trans. Knowl. Data Eng. 24(11), 2080–2093 (2012)

    Article  Google Scholar 

  2. Choromański, M., Grześ, T., Hońko, P.: Breadth search strategies for finding minimal reducts - towards hardware implementation. Neural Comput. Appl. (2019, under review)

    Google Scholar 

  3. Degang, C., Changzhong, W., Qinghua, H.: A new approach to attribute reduction of consistent and inconsistent covering decision systems with covering rough sets. Inf. Sci. 177(17), 3500–3518 (2007)

    Article  MathSciNet  Google Scholar 

  4. Grześ, T., Kopczyński, M., Stepaniuk, J.: FPGA in rough set based core and reduct computation. In: Lingras, P., Wolski, M., Cornelis, C., Mitra, S., Wasilewski, P. (eds.) RSKT 2013. LNCS (LNAI), vol. 8171, pp. 263–270. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-41299-8_25

    Chapter  Google Scholar 

  5. Kopczyński, M., Grześ, T., Stepaniuk, J.: FPGA in rough-granular computing: reduct generation. In: Proceedings of the 2014 IEEE/WIC/ACM International Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (IAT) - Volume 02, WI-IAT 2014, pp. 364–370. IEEE Computer Society, Washington (2014)

    Google Scholar 

  6. Pawlak, Z.: Rough Sets. Theoretical Aspects of Reasoning about Data. Kluwer Academic, Dordrecht (1991)

    MATH  Google Scholar 

  7. Skowron, A., Rauszer, C.: The discernibility matrices and functions in information systems. In: Słowiński, R. (ed.) Intelligent Decision Support. Theory and Decision Library (Series D: System Theory, Knowledge Engineering and Problem Solving), vol. 11, pp. 331–362. Springer, Dordrecht (1992). https://doi.org/10.1007/978-94-015-7975-9_21

    Chapter  Google Scholar 

  8. Stepaniuk, J.: Rough set data mining of diabetes data. In: Raś, Z.W., Skowron, A. (eds.) ISMIS 1999. LNCS, vol. 1609, pp. 457–465. Springer, Heidelberg (1999). https://doi.org/10.1007/BFb0095133

    Chapter  Google Scholar 

  9. Stepaniuk, J.: Rough-Granular Computing in Knowledge Discovery and Data Mining. Studies in Computational Intelligence, vol. 152. Springer-Verlag, Heidelberg (2008). https://doi.org/10.1007/978-3-540-70801-8

    Book  MATH  Google Scholar 

  10. Sun, G., Qi, X., Zhang, Y.: A FPGA-based implementation of rough set theory. In: 2011 Chinese Control and Decision Conference (CCDC), pp. 2561–2564 (2011)

    Google Scholar 

  11. Swiniarski, R.: Rough sets methods in feature reduction and classification. Int. J. Appl. Math. Comput. Sci. 11(3), 565–582 (2001)

    MathSciNet  MATH  Google Scholar 

  12. Swiniarski, R.W., Skowron, A.: Rough set methods in feature selection and recognition. Pattern Recogn. Lett. 24(6), 833–849 (2003)

    Article  Google Scholar 

  13. Thi, V.D., Giang, N.L.: A method for extracting knowledge from decision tables in terms of functional dependencies. Cybern. Inf. Technol. 13(1), 73–82 (2013)

    MathSciNet  Google Scholar 

  14. Tiwari, K.S., Kothari, A.G.: Architecture and implementation of attribute reduction algorithm using binary discernibility matrix. In: 2011 International Conference on Computational Intelligence and Communication Networks, pp. 212–216 (2011)

    Google Scholar 

  15. Tiwari, K., Kothari, A.: Design and implementation of rough set co-processor on FPGA. Int. J. Innovative Comput. Inf. Control 11(2), 641–656 (2015)

    Google Scholar 

  16. Tiwari, K., Kothari, A.: Design of intelligent system for medical applications using rough set theory. Int. J. Data Min. Model. Manag. 8(3), 279–301 (2016)

    Google Scholar 

  17. Zhang, X., Mei, C., Chen, D., Li, J.: Multi-confidence rule acquisition oriented attribute reduction of covering decision systems via combinatorial optimization. Knowl.-Based Syst. 50, 187–197 (2013)

    Article  Google Scholar 

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Authors and Affiliations

  1. Faculty of Computer Science, Białystok University of Technology, Wiejska 45A, 15-351, Białystok, Poland

    Mateusz Choromański, Tomasz Grześ & Piotr Hońko

Authors
  1. Mateusz Choromański
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  2. Tomasz Grześ
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  3. Piotr Hońko
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Corresponding author

Correspondence to Mateusz Choromański .

Editor information

Editors and Affiliations

  1. Bialystok University of Technology, Bialystok, Poland

    Khalid Saeed

  2. University of Calcutta, Calcutta, India

    Rituparna Chaki

  3. Mihajlo Pupin Institute, Belgrade, Serbia

    Valentina Janev

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Choromański, M., Grześ, T., Hońko, P. (2019). Two FPGA Devices in the Problem of Finding Minimal Reducts. In: Saeed, K., Chaki, R., Janev, V. (eds) Computer Information Systems and Industrial Management. CISIM 2019. Lecture Notes in Computer Science(), vol 11703. Springer, Cham. https://doi.org/10.1007/978-3-030-28957-7_34

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  • DOI: https://doi.org/10.1007/978-3-030-28957-7_34

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-28956-0

  • Online ISBN: 978-3-030-28957-7

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