Abstract
We implement the Grain-128AEAD stream cipher in hardware, using a 65 nm library. By exploring different optimization techniques, both at RTL level but also during synthesis, we first target high throughput, then low power. We reach over 33 GB/s targeting a high-speed design, at expense of power and area. We also show that, when targeting low power, the design only requires 0.23 \({\upmu }\)W running at 100 kHz. By unrolling the design, the energy consumed when encrypting a fixed length message decreases, making the 64 parallelized version the most energy efficient implementation, requiring only 11.2 nJ when encrypting a 64 kbit message. At the same time, the best throughput/power ratio is achieved at a parallelization of 4.
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This paper was supported by the Swedish Foundation for Strategic Research, grant RIT17-0032.
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Sönnerup, J., Hell, M., Sönnerup, M., Khattar, R. (2019). Efficient Hardware Implementations of Grain-128AEAD. In: Hao, F., Ruj, S., Sen Gupta, S. (eds) Progress in Cryptology – INDOCRYPT 2019. INDOCRYPT 2019. Lecture Notes in Computer Science(), vol 11898. Springer, Cham. https://doi.org/10.1007/978-3-030-35423-7_25
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DOI: https://doi.org/10.1007/978-3-030-35423-7_25
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