Abstract
Frame jitter occurs when the delay between a trigger and the start of a signal acquisition or signal generation is different among subsequence data frames. Test bench waveform signal generators features low frame jitter (e.g. 400 ps rms), but this performance is still insufficient for the instrument to be used in sensitive applications like Doppler velocimetry. In this work a circuit is presented that synchronizes on-the-fly an internal clock to every occurrence of an external trigger. It is implemented in a Field Programmable Gate Array (FPGA) and features a frame jitter lower than 100 ps rms.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Kalashnikov AN, Challis RE, Unwin ME, Holmes AK (2005) Effects of frame jitter in data acquisition systems. IEEE Trans Instrum Meas 54(6):2177–2183. https://doi.org/10.1109/TIM.2005.858570
Pieraccini M, Miccinesi L (2019) Ground-based radar interferometry: a bibliographic review. Remote Sens 11(9):1029. https://doi.org/10.3390/rs11091029
Ricci S, Ramalli A, Bassi L, Boni E, Tortoli P (2018) Real-time blood velocity vector measurement over a 2D region. IEEE Trans Ultrason Ferroelect Freq Control 65(2):201–209. https://doi.org/10.1109/TUFFC.2017.2781715
Birkhofer B, Debacker A, Russo S, Ricci S, Lootens D (2012) In-line rheometry based on ultrasonic velocity profiles: comparison of data processing methods. Appl Rheol 22(4):44701. https://doi.org/10.3933/ApplRheol-22-44701
Cyclone III Device Handbook, CIII 5V1-4.2, Altera Corp (2012)
Roberts GW, Ali-Bakhshian M (2010) A brief introduction to time-to-digital and digital-to-time converters. IEEE Trans Circ Syst II-Express Briefs 57(3):153–157. https://doi.org/10.1109/TCSII.2010.2043382
Dadouche F, Turko T, Uhring W, Malass I, Dumas N, Le Normand JP (2015) New design-methodology of high-performance TDC on a low cost FPGA targets. Sens Transducers J 193(10):123–134
Wu J (2010) Several key issues on implementing delay line based TDCs using FPGAs. IEEE Trans Nucl Sci 57(3):1543–1548. https://doi.org/10.1109/TNS.2010.2045901
Ricci S, Meacci V, Birkhofer B, Wiklund J (2017) FPGA-based system for in-line measurement of velocity profiles of fluids in industrial pipe flow. IEEE Trans Ind Electron 64(5):3997–4005. https://doi.org/10.1109/TIE.2016.2645503
Ricci S, Vilkomerson D, Matera R, Tortoli P (2015) Accurate blood peak velocity estimation using spectral models and vector doppler. IEEE Trans Ultrason Ferroelect Freq Control 62(4):686–696. https://doi.org/10.1109/TUFFC.2015.006982
Marino-Merlo E, Bulletti A, Giannelli P, Calzolai M, Capineri L (2018) Analysis of errors in the estimation of impact positions in plate-like structure through the triangulation formula by piezoelectric sensors monitoring. Sensors 18(10):E3426. https://doi.org/10.3390/s18103426
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Russo, D., Ricci, S. (2020). FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2019. Lecture Notes in Electrical Engineering, vol 627. Springer, Cham. https://doi.org/10.1007/978-3-030-37277-4_23
Download citation
DOI: https://doi.org/10.1007/978-3-030-37277-4_23
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-37276-7
Online ISBN: 978-3-030-37277-4
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)