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Flexible Data Flow Architecture for Embedded Hardware Accelerators

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Algorithms and Architectures for Parallel Processing (ICA3PP 2019)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 11944))

Abstract

In order to enable control units to run future algorithms, such as advanced control theory, advanced signal processing, data-based modeling, and physical modeling, the control units require a substantial step-up in computational power. In case of an automotive Engine Control Unit (ECU), safety requirements and cost constraints are just as important. Existing solutions to increase the performance of a microcontroller are either not suitable for a subset of the expected algorithms, or too expensive in terms of area. Hence, we introduce the novel Data Flow Architecture (DFA) for embedded hardware accelerators. The DFA is flexible from the concept level to the individual functional units to achieve a high performance per size ratio for a wide variety of data intensive algorithms. Compared to hardwired implementations, the area can be as little as 1.4 times higher at the same performance.

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Authors and Affiliations

  1. Robert Bosch GmbH, 70442, Stuttgart, Germany

    Jens Froemmer, Nico Bannow & Axel Aue

  2. University of Kaiserslautern, 67663, Kaiserslautern, Germany

    Jens Froemmer, Christoph Grimm & Klaus Schneider

Authors
  1. Jens Froemmer
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  2. Nico Bannow
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  3. Axel Aue
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  4. Christoph Grimm
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  5. Klaus Schneider
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Corresponding author

Correspondence to Jens Froemmer .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Software Engineering, Swinburne University of Technology, Hawthorn, Melbourne, VIC, Australia

    Sheng Wen

  2. School of Computer Science, The University of Sydney, Camperdown, NSW, Australia

    Albert Zomaya

  3. Department of Computer Science, St. Francis Xavier University, Antigonish, NS, Canada

    Laurence T. Yang

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Froemmer, J., Bannow, N., Aue, A., Grimm, C., Schneider, K. (2020). Flexible Data Flow Architecture for Embedded Hardware Accelerators. In: Wen, S., Zomaya, A., Yang, L. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2019. Lecture Notes in Computer Science(), vol 11944. Springer, Cham. https://doi.org/10.1007/978-3-030-38991-8_3

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