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Evaluating Cache Line Behavior Predictors for Energy Efficient Processors

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High Performance Computing Systems (WSCAD 2018)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1171))

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Abstract

The ever-increasing size of cache memories, nowadays achieving almost half of the area for modern processors, and so essential to the performance of the systems, are leading into a crescent static energy consumption. In order to save some of this energy and optimize its component performance, many techniques were proposed. Cache line reuse predictors and dead line predictors are some examples. These mechanisms predict whenever a cache line shall be dead, in order to turn it off, also applying other policies on them, such as replacement prioritization or bypassing its installation inside the cache. However, not all mechanisms implement all these policies, that directly affect the cache behavior in different ways. This paper evaluates the impacts of the priority and bypass policies over two dead line predictors, the Dead Block and Early Write Back Predictor (DEWP) and the Skewed Dead Block predictor (SDP). Both mechanisms turn off dead cache lines using Gated-Vdd technique in order to save their static energy, thus analyzing how each policy (Priority replacement and cache Bypass) affects the energy savings and the system performance.

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References

  1. Alves, M.A.Z.: Increasing energy efficiency of processor caches via line usage predictors. Ph.D. thesis, UFRGS, Porto Alegre (2014)

    Google Scholar 

  2. Alves, M.A.Z., Villavieja, C., Diener, M., Navaux, P.O.A.: Energy efficient last level caches via last read/write prediction. In: International Symposium on Computer Architecture and High Performance Computing, pp. 73–80 (2013)

    Google Scholar 

  3. Beckmann, N., Sanchez, D.: Maximizing cache performance under uncertainty. In: International Symposium on High Performance Computer Architecture, pp. 109–120 (2017)

    Google Scholar 

  4. Chi, C., Dietz, H.: Improving cache performance by selective cache bypass. In: International Conference on System Sciences, pp. 277–285 (1989)

    Google Scholar 

  5. Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.: Gated-Vdd : a circuit technique to reduce leakage in deep-submicron cache memories. In: International Symposium on Low Power Electronics and Design, Digest of Technical Papers, pp. 90–95 (2000)

    Google Scholar 

  6. Faldu, P., Grot, B.: Leeway: addressing variability in dead-block prediction for last-level caches. In: International Conference on Parallel Architectures and Compilation Techniques, pp. 180–193 (2017)

    Google Scholar 

  7. Henning, J.L.: Spec cpu2006 benchmark descriptions. SIGARCH Comput. Archit. News 34(4), 1–17 (2006)

    Article  Google Scholar 

  8. Jain, A., Lin, C.: Back to the future: leveraging Belady’s algorithm for improved cache replacement. In: International Symposium on Computer Architecture, pp. 78–89 (2016)

    Google Scholar 

  9. Jaleel, A., Theobald, K.B., Steely Jr., S.C., Emer, J.: High performance cache replacement using re-reference interval prediction (RRIP). ACM SIGARCH Comput. Archit. News. 38, 60–71 (2010)

    Article  Google Scholar 

  10. Jiménez, D.A., Teran, E.: Multiperspective reuse prediction. In: International Symposium on Microarchitecture, pp. 436–448 (2017)

    Google Scholar 

  11. Jiménez, D.A.: Insertion and promotion for tree-based PseudoLRU last-level caches. In: International Symposium on Microarchitecture, pp. 284–296 (2013)

    Google Scholar 

  12. Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: International Symposium on Computer Architecture, pp. 240–251 (2001)

    Google Scholar 

  13. Khan, S., Burger, D., Jiménez, D.A., Falsafi, B.: Using dead blocks as a virtual victim cache. In: International Conference on Parallel Architectures and Compilation Techniques, pp. 489–500 (2010)

    Google Scholar 

  14. Khan, S.M., Tian, Y., Jimenez, D.A.: Sampling dead block prediction for last-level caches. In: International Symposium on Microarchitecture, pp. 175–186 (2010)

    Google Scholar 

  15. Kharbutli, M., Solihin, Y.: Counter-based cache replacement and bypassing algorithms. IEEE Trans. Comput. 57(4), 433–447 (2008)

    Article  MathSciNet  Google Scholar 

  16. Lee, H., Jin, L., Lee, K., Demetriades, S., Moeng, M., Cho, S.: Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. Softw. Pract. Exp. 40(3), 239–258 (2010)

    Google Scholar 

  17. Sokulski, R.M., Carreno, E.D., Alves, M.A.: Evaluating dead line predictors efficiency with drowsy technique. In: Brazilian Symposium on Computing Systems Engineering, pp. 250–255 (2018)

    Google Scholar 

  18. Sokulski, R., Carreno, E., Alves, M.: Introducing drowsy technique to cache line usage predictors. In: Brazilian Symposium on Computing Systems, pp. 259–265 (2018)

    Google Scholar 

  19. Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: Architecting efficient interconnects for large caches with cacti 6.0. IEEE Micro 28, 69–79 (2008)

    Article  Google Scholar 

  20. Patil, H., Cohn, R., et al.: Pinpointing representative portions of large intel ® itanium ® programs with dynamic instrumentation. In: International Symposium on Microarchitecture, pp. 81–92 (2004)

    Google Scholar 

  21. Pekhimenko, G., et al.: Exploiting compressed block size as an indicator of future reuse. In: International Symposium on High Performance Computer Architecture, pp. 51–63 (2015)

    Google Scholar 

  22. Powell, M., Yang, S.H., et al.: Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: International Symposium on Low Power Electronics and Design, pp. 90–95 (2000)

    Google Scholar 

  23. Seznec, A.: A case for two-way skewed-associative caches. In: International Symposium on Computer Architecture (1993)

    Google Scholar 

  24. Teran, E., Wang, Z., Jimenez, D.A.: Perceptron learning for reuse prediction. In: International Symposium on Microarchitecture, pp. 1–12 (2016)

    Google Scholar 

  25. Vakil-Ghahani, A., Mahdizadeh-Shahri, S., et al.: Cache replacement policy based on expected hit count. IEEE Comput. Archit. Lett. 17(1), 64–67 (2018)

    Article  Google Scholar 

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Authors and Affiliations

  1. Federal University of Paraná, Curitiba, PR, Brazil

    Rodrigo Machniewicz Sokulski, Emmanuell Diaz Carreno & Marco Antonio Zanata Alves

Authors
  1. Rodrigo Machniewicz Sokulski
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  2. Emmanuell Diaz Carreno
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  3. Marco Antonio Zanata Alves
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Corresponding author

Correspondence to Rodrigo Machniewicz Sokulski .

Editor information

Editors and Affiliations

  1. Mackenzie Presbyterian University, São Paulo, Brazil

    Calebe Bianchini

  2. National Laboratory for Scientific Computing, Rio de Janeiro, Brazil

    Carla Osthoff

  3. University of São Paulo, São Paulo, Brazil

    Paulo Souza

  4. Federal University of Minas Gerais, Belo Horizonte, Brazil

    Renato Ferreira

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Sokulski, R.M., Carreno, E.D., Alves, M.A.Z. (2020). Evaluating Cache Line Behavior Predictors for Energy Efficient Processors. In: Bianchini, C., Osthoff, C., Souza, P., Ferreira, R. (eds) High Performance Computing Systems. WSCAD 2018. Communications in Computer and Information Science, vol 1171. Springer, Cham. https://doi.org/10.1007/978-3-030-41050-6_12

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  • DOI: https://doi.org/10.1007/978-3-030-41050-6_12

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-41049-0

  • Online ISBN: 978-3-030-41050-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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