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Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP)

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Abstract

With the rapid development of the fifth-generation mobile communication technology (5G), existing digital signal processors (DSP) on the market cannot efficiently provide the performance required by some applications. In this situation, we design a new DSP with faster speed, lower latency and higher performance. In this article, based on the new DSP which can adapt to the new technology of 5G, we designed an assembler called Swift Assembler (SA). Different from the traditional assembler, SA is based on the Gnu Architecture Description Language, (GADL). We perform semantic analysis on GADL description files and then with the help of flex, bison and Binutils, the assembler is compiled and generated. With the support of GADL, SA has a clearer architecture and better scalability. At the same time, it covered the underlying implementation. Benefit from this, programmers can modify its source code with no need to understand the underlying implementation process. In this way, the design of interdependent hardware and software can be more easily.

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References

  1. Ji, X., Huang, K., Jin, L., Tang, H., Liu, C., et al.: Overview of 5G security technology. Sci. China (Inf. Sci.) 61(08), 107–131 (2018)

    Google Scholar 

  2. GNU Binary Utilities. http://www.sourceware.org/binutils/

  3. Clements, P.C.: A survey of architecture description languages. In: Proceedings of the Software Specification and Design. IEEE Computer Society, April 1996. https://doi.org/10.1109/iwssd.1996.501143

  4. Shen, J.: A research on processor architecture description languages and implementation of tool-chain generation (unpublished)

    Google Scholar 

  5. McCarthy, J.: Recursive functions of symbolic expressions and their computation by machine. Technical report, Massachusetts Institute of Technology, Cambridge, MA, USA

    Google Scholar 

  6. Lin, T.J., Chen, S.K., Kuo, Y.T., et al.: Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications. J. Sig. Process. Syst. 51(3), 209–223 (2008)

    Article  Google Scholar 

  7. Hu, Y., Chen, S.: Preprocessing scheme of intelligent assembly for a high performance VLIW DSP. In: Second International Conference on Cloud & Green Computing (2013)

    Google Scholar 

  8. Hadjiyiannis, G., Hanono, S., Decadas, S.: ISDL: an instruction set description set processors for retargetability. In: Proceedings of the 34th Annual Design Automation Conference, pp. 299–302. ACM (1997)

    Google Scholar 

  9. Freericks, M.: The nML machine description formalism

    Google Scholar 

  10. Fau, A., Van Praet, J., Freericks, M.: Description instruction set processors using nML. In: Proceedings of the European Design and Test Conference, ED&TC 1995, pp. 503–507. IEEE (1995)

    Google Scholar 

  11. The Fast Lexical Analyzer. http://flex.sourceforge.net/

  12. GNU Bison. http://www.gnu.org/software/bison/

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Acknowledgment

The authors thank the editors and the anonymous reviewers for their invaluable comments to help to improve the quality of this paper. This work was supported in part by the National Natural Science Foundation of China under Grant Nos. 61831018, 61571329 and 61631017, and Guangdong Province Key Research and Development Program Major Science and Technology Projects under Grant 2018B010115002.

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Correspondence to Jun Wu .

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© 2020 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Ding, P., Ren, H., Zhang, Z., Wu, J., Zhu, F., Zhang, W. (2020). Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP). In: Gao, H., Feng, Z., Yu, J., Wu, J. (eds) Communications and Networking. ChinaCom 2019. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 312. Springer, Cham. https://doi.org/10.1007/978-3-030-41114-5_56

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  • DOI: https://doi.org/10.1007/978-3-030-41114-5_56

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-41113-8

  • Online ISBN: 978-3-030-41114-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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