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International Conference on Smart Card Research and Advanced Applications

CARDIS 2019: Smart Card Research and Advanced Applications pp 20–39Cite as

Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 11833))

Abstract

Threshold implementations have emerged as one of the most popular masking countermeasures for hardware implementations of cryptographic primitives. In this work, we first provide a generic construction for \(d+1\) TI sharing which achieves the minimal number of output shares for any n-input Boolean function of degree \(t=n-1\) and for any d. Secondly, we demonstrate the applicability of our results on a first-order and second-order \(d+1\) low-latency PRINCE implementation.

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Acknowledgements

We would like to thank Amir Moradi and Tobias Schneider for providing us with HDL code of PRINCE TI presented in [14]. Also we would like to thank the reviewers for helping us to improve the paper.

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Authors and Affiliations

  1. NXP Semiconductors, Leuven, Belgium

    Dušan Božilov, Miroslav Knežević & Ventzislav Nikov

  2. COSIC KU Leuven and imec, Leuven, Belgium

    Dušan Božilov

Authors
  1. Dušan Božilov
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  2. Miroslav Knežević
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  3. Ventzislav Nikov
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Corresponding author

Correspondence to Dušan Božilov .

Editor information

Editors and Affiliations

  1. CryptoExperts, Paris, France

    Sonia Belaïd

  2. Ruhr-Universität Bochum, Bochum, Germany

    Tim Güneysu

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Božilov, D., Knežević, M., Nikov, V. (2020). Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators. In: Belaïd, S., Güneysu, T. (eds) Smart Card Research and Advanced Applications. CARDIS 2019. Lecture Notes in Computer Science(), vol 11833. Springer, Cham. https://doi.org/10.1007/978-3-030-42068-0_2

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  • DOI: https://doi.org/10.1007/978-3-030-42068-0_2

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-42067-3

  • Online ISBN: 978-3-030-42068-0

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