Abstract
The code synthesis, especially the multi-task code generation, plays an important role in the implementation of the safety-critical applications. MiniSIGNAL is a sequential/multi-task code generation tool for the synchronous language SIGNAL. During the application of real-world industrial case study, we find the generated programs is still inefficient due to a shortage of the original code generation strategies. Therefore, this paper presents a new multi-task code generation method for SIGNAL. Starting at the level of synchronous clocked guarded actions (S-CGA) which is an intermediate language for the compilation process of MiniSIGNAL, the transformation consists of two levels: At the platform-independent level, transforming the S-CGA code to an abstract multi-task structure (called VMT) with formal syntax and semantics; At the platform-dependent level, adopting the thread pool pattern to implement parallel Ada code generated from the VMT structure. The approach is applied to a real-world Guidance, Navigation and Control system to show the effectiveness of our approach.
Supported by organization by the National Natural Science Foundation of China (61502231); The National Key Research and Development Program of China (2016YFB1000802); The Natural Science Foundation of Jiangsu Province (BK20150753); The National Defense Basic Scientific Research Project under Grant of China (JCKY2016203B011); The Fundamental Research Funds for the Central Universities (NP2017205); the Foundation of Graduate Innovation Center in NUAA (kfjj20181603).
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References
Baudisch, D., Brandt, J., Schneider, K.: Multithreaded code from synchronous programs: extracting independent threads for OpenMP. In: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 949–952. IEEE (2010)
Baudisch, D., Brandt, J., Schneider, K.: Multithreaded code from synchronous programs: generating software pipelines for OpenMP. In: MBMV, pp. 11–20 (2010)
Berry, G.: Synchronous design and verification of critical embedded systems using SCADE and Esterel. In: Leue, S., Merino, P. (eds.) FMICS 2007. LNCS, vol. 4916, p. 2. Springer, Heidelberg (2008). https://doi.org/10.1007/978-3-540-79707-4_2
Besnard, L., Gautier, T., Talpin, J.P.: Code generation strategies in the Polychrony environment. Research Report RR-6894, INRIA (2009)
Bourke, T., Brun, L., Dagand, P.E., Leroy, X., Pouzet, M., Rieg, L.: A formally verified compiler for Lustre. In: 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, Barcelone, Spain. ACM, June 2017
Boussinot, F., De Simone, R.: The ESTEREL language. Proc. IEEE 79(9), 1293–1304 (1991)
Colaço, J.L., Pagano, B., Pasteur, C., Pouzet, M.: Scade 6: from a Kahn semantics to a Kahn implementation for multicore. In: 2018 Forum on Specification & Design Languages (FDL), pp. 5–16. IEEE (2018)
Feiler, P.H., Gluch, D.P.: Model-Based Engineering with AADL: An Introduction to the SAE Architecture Analysis & Design Language. Pearson Schweiz AG, Zug (2013)
Ferrell, T.K., Ferrell, U.D.: RTCA DO-178C/EUROCAE ED-12C. In: Digital Avionics Handbook (2017)
Giannopoulou, G., et al.: DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. Des. Autom. Embed. Syst. 22(1), 141–181 (2018). https://doi.org/10.1007/s10617-018-9206-3
Hu, K., Zhang, T., Shang, L., Yang, Z., Talpin, J.P.: Parallel code generation from synchronous specification. J. Softw. 28, 1–15 (2017)
Jose, B.A., Patel, H.D., Shukla, S.K., Talpin, J.P.: Generating multi-threaded code from polychronous specifications. Electron. Notes Theor. Comput. Sci. 238(1), 57–69 (2009)
Krebs, F.: A translation framework from RVC-CAL dataflow programs to OpenCL/SYCL based implementations. Master’s thesis, Department of Computer Science, University of Kaiserslautern, Germany, January 2019
Li, Z., et al.: Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. J. Syst. Architect. 74, 30–45 (2017)
Rafique, O., Krebs, F., Schneider, K.: Generating efficient parallel code from the RVC-CAL dataflow language. In: Euromicro Conference on Digital System Design (DSD), Kallithea, Chalkidiki, Greece. IEEE Computer Society (2019)
Shi, G., Zhang, Y., Shang, S., Wang, S., Dong, Y., Yew, P.C.: A formally verified transformation to unify multiple nested clocks for a lustre-like language. Sci. China Inf. Sci. 62(1), 12801 (2019)
Souyris, J., et al.: Automatic parallelization from Lustre models in avionics. In: ERTS2 2018-9th European Congress Embedded Real-Time Software and Systems, pp. 1–4 (2018)
Yang, Z., Bodeveix, J.P., Filali, M.: Towards a simple and safe Objective Caml compiling framework for the synchronous language SIGNAL. Front. Comput. Sci. 13(4), 715–734 (2019). https://doi.org/10.1007/s11704-017-6485-y
Yang, Z., Bodeveix, J.P., Filali, M., Hu, K., Zhao, Y., Ma, D.: Towards a verified compiler prototype for the synchronous language SIGNAL. Front. Comput. Sci. 10(1), 37–53 (2016). https://doi.org/10.1007/s11704-015-4364-y
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Yuan, S., Yang, Z., Bodeveix, JP., Filali, M., Wang, T., Zhou, Y. (2020). Automated Ada Code Generation from Synchronous Dataflow Programs on Multicore: Approach and Industrial Study. In: Hasan, O., Mallet, F. (eds) Formal Techniques for Safety-Critical Systems. FTSCS 2019. Communications in Computer and Information Science, vol 1165. Springer, Cham. https://doi.org/10.1007/978-3-030-46902-3_4
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