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The Synthesis Method of High-Speed Finite State Machines in FPGA

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Computer Information Systems and Industrial Management (CISIM 2020)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 12133))

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Abstract

The synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

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References

  1. Miyazaki, N., Nakada, H., Tsutsui, A., Yamada, K., Ohta, N.: Performance improvement technique for synchronous circuits realized as LUT-Based FPGA’s. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3(3), 455–459 (1995)

    Google Scholar 

  2. Jozwiak, L., Slusarczyk, A., Chojnacki, A.: Fast and compact sequential circuits through the information-driven circuit synthesis. In: Proceedings of the Euromicro Symposium on Digital Systems Design, Warsaw, Poland, 4–6 September 2001, pp. 46–53 (2001)

    Google Scholar 

  3. Huang, S.-Y.: On speeding up extended finite state machines using catalyst circuitry. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASAP-DAC), Yokohama, January-February, 2001, pp. 583–588 (2001)

    Google Scholar 

  4. Kuusilinna, K., Lahtinen, V., Hamalainen, T., Saarinen, J.: Finite state machine encoding for VHDL synthesis. Comput. Dig. Techniques, IEE Proc. 148(1), 23–30 (2001)

    Article  Google Scholar 

  5. Rafla, N.I., Davis, B.A.: Study of finite state machine coding styles for implementation in FPGAs. In: Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, USA, 6–9 August 2006, vol. 1, pp. 337–341 (2006)

    Google Scholar 

  6. Nedjah, N., Mourelle, L.: Evolutionary synthesis of synchronous finite state machines. In: Proceedings of the International Conference on Computer Engineering and Systems, Cairo, Egypt, 5–7 November 2006, pp. 19–24 (2006)

    Google Scholar 

  7. Czerwiński, R., Kania, D.: Synthesis method of high speed finite state machines. Bull. Polish Acad. Sci. Techn. Sci. 58(4), 635–644 (2010)

    Google Scholar 

  8. Glaser, J., Damm, M., Haase, J., Grimm, C.: TR-FSM: transition-based reconfigurable finite state machine. ACM Trans. Reconfigurable Technol. Syst. (TRETS) 4(3), 231–2314 (2011)

    Google Scholar 

  9. Senhadji-Navarro, R., Garcia-Vargas, I.: Finite virtual state machines. IEICE Trans. Inf. Syst. E95D(10), 2544–2547 (2012)

    Article  Google Scholar 

  10. Garcia-Vargas, I., Senhadji-Navarro, R.: Finite state machines with input multiplexing: a performance study. IEEE Trans. Computer-aided Design Integr. Circ. Syst. 34(5), 867–871 (2015)

    Article  Google Scholar 

  11. Solov’ev, V.V.: Splitting the internal states in order to reduce the number of arguments in functions of finite automata. J. Comput. Syst. Sci. Int. 44(5), 777–783 (2005)

    MATH  Google Scholar 

  12. Yang, S.: Logic synthesis and optimization benchmarks user guide. Version 3.0. Microelectronics Center of North Carolina (MCNC). North Carolina, USA (1991)

    Google Scholar 

  13. Lin, B., Newton, A.R.: Synthesis of multiple level logic from symbolic high-level description languages. In: Proceedings of the International Conference on VLSI, 1989, Munich, pp. 187–196 (1989)

    Google Scholar 

  14. Villa, T., Sangiovanni-Vincentelli, A.: Nova: state assignment of finite state machines for optimal two-level logic implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9), 905–924 (1990)

    Article  Google Scholar 

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Correspondence to Valery Salauyou .

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Salauyou, V., Borecki, D., Grzes, T. (2020). The Synthesis Method of High-Speed Finite State Machines in FPGA. In: Saeed, K., Dvorský, J. (eds) Computer Information Systems and Industrial Management. CISIM 2020. Lecture Notes in Computer Science(), vol 12133. Springer, Cham. https://doi.org/10.1007/978-3-030-47679-3_9

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  • DOI: https://doi.org/10.1007/978-3-030-47679-3_9

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-47678-6

  • Online ISBN: 978-3-030-47679-3

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