Abstract
The synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.
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Salauyou, V., Borecki, D., Grzes, T. (2020). The Synthesis Method of High-Speed Finite State Machines in FPGA. In: Saeed, K., Dvorský, J. (eds) Computer Information Systems and Industrial Management. CISIM 2020. Lecture Notes in Computer Science(), vol 12133. Springer, Cham. https://doi.org/10.1007/978-3-030-47679-3_9
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