Abstract
In this paper, we argue that there are two fundamental ways of defining correctness of concurrent objects on the weak memory models of multicore processors: we can abstract from concurrent interleaving and weak memory effects at the specification level, or we can abstract from concurrent interleaving only, leaving weak memory effects at the specification level. The first allows us to employ standard linearizability as the correctness criterion; a result proved in earlier work. The second requires a weakening of linearizability. We provide such a weakening and prove it sound and complete with respect to this notion of correctness.
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- 1.
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This is no longer true for the latest version of ARMv8 [20].
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Since there is at most one pending invocation per thread, such an \(h'\) will be in the prefix-closed set .
- 4.
A control fence (ctrl_isync in ARM and denoted cfence in Fig. 1) ensures that all branch instructions occurring before it take effect before any loads, i.e., reads of global variables, occurring after it.
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Acknowledgement
Thanks to Kirsten Winter for fruitful discussions on this topic. This work was supported by Australian Research Council Discovery Grant DP160102457.
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Smith, G., Groves, L. (2020). Weakening Correctness and Linearizability for Concurrent Objects on Multicore Processors. In: Sekerinski, E., et al. Formal Methods. FM 2019 International Workshops. FM 2019. Lecture Notes in Computer Science(), vol 12233. Springer, Cham. https://doi.org/10.1007/978-3-030-54997-8_22
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