Abstract
Real-time systems are subject to strong timing requirements, and thus rely on worst-case timing analyses to safely address them. Undesired timing phenomena, called timing anomalies, threaten the soundness of timing analyses. In this regard, we consider the following inauspicious partnership - a compositional timing analysis and amplification timing anomalies. Precisely, we investigate how the industrial, superscalar TriCore architecture is amenable for compositional timing analyses via a formal evaluation of amplification timing anomalies. We adapt and extend a specialized abstraction, called canonical pipeline model, to quantify the amplification effects in a model of a dual-pipelined TriCore, its asynchronous store buffer, data dependencies, and structural hazards. We use model checking to efficiently detect amplification timing anomalies and report the associated complexity results.
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References
Asavoae, M., Hedia, B.B., Jan, M.: Formal executable models for automatic detection of timing anomalies. In: 18th International Workshop on Worst-Case Execution Time Analysis (WCET), Barcelona, Spain, pp. 2:1–2:13 (2018)
Ballabriga, C., Cassé, H., Rochange, C., Sainrat, P.: OTAWA: an open toolbox for adaptive WCET analysis. In: Min, S.L., Pettit, R., Puschner, P., Ungerer, T. (eds.) SEUS 2010. LNCS, vol. 6399, pp. 35–46. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-16256-5_6
Binder, B., Jan, M.: UCLID5 model for tricore (2020). https://github.com/t-crest/patmos-sail/tree/master/uclid/tricore
de Dinechin, B.D., van Amstel, D., Poulhiès, M., Lager, G.: Time-critical computing on a single-chip massively parallel processor. In: Proceedings of the Conference on Design, Automation & Test in Europe (DATE 2014), pp. 97:1–97:6 (2014)
Eisinger, J., Polian, I., Becker, B., Metzner, A., Thesing, S., Wilhelm, R.: Automatic identification of timing anomalies for cycle-accurate worst-case execution time analysis. In: Proceedings of the Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS), Prague, Czech Republic, pp. 15–20, April 2006
Hahn, S., Reineke, J.: Design and analysis of SIC: a provably timing-predictable pipelined processor core. In: 2018 IEEE Real-Time Systems Symposium (RTSS), pp. 469–481, December 2018
Hahn, S., Jacobs, M., Reineke, J.: Enabling compositionality for multicore timing analysis. In: Plantec, A., Singhoff, F., Faucou, S., Pinho, L.M. (eds.) Proceedings of the 24th International Conference on Real-Time Networks and Systems, RTNS 2016, Brest, France, 19–21 October 2016, pp. 299–308. ACM (2016)
Hahn, S., Reineke, J., Wilhelm, R.: Towards compositionality in execution time analysis: definition and challenges. SIGBED Rev. 12(1), 28–36 (2015)
Infineon Technologies AG: TriCore 1 Pipeline Behaviour and Instruction Execution Timing, June 2004
Infineon Technologies AG: AURIX TC21x/TC22x/TC23x Family 32-Bit Single-Chip Microcontroller User’s Manual, December 2014
Jan, M., Asavoae, M., Schoeberl, M., Lee, E.: Formal semantics of predictable pipelines: a comparative study. In: Proceedings of the 25th Asia and South Pacific Design Automation Conference, United States. IEEE (2020)
Liu, I., Reineke, J., Lee, E.A.: A PRET architecture supporting concurrent programs with composable timing properties. In: 44th Asilomar Conference on Signals, Systems, and Computers, November 2010
Lundqvist, T., Stenstrom, P.: Timing anomalies in dynamically scheduled microprocessors, pp. 12–21, December 1999
Nguyen, V.A., Jenn, E., Serwe, W., Lang, F., Mateescu, R.: Using model checking to identify timing interferences on multicore processors. In: ERTS 2020–10th European Congress on Embedded Real Time Software and Systems, Toulouse, France, pp. 1–10 (2020)
Reineke, J., et al.: A definition and classification of timing anomalies. In: 6th International Workshop on Worst-Case Execution Time (WCET) Analysis, Dresden, Germany, July 2006
Schoeberl, M., et al.: T-CREST: time-predictable multi-core architecture for embedded systems. J. Syst. Arch. Embed. Syst. Des. 61(9), 449–471 (2015)
Seshia, S., Subramanyan, P.: UCLID 5: integrating modeling, verification, synthesis and learning, pp. 1–10, December 2018
Sun, W.T., Jenn, E., Cassé, H.: Build your own static WCET analyser: the case of the automotive processor AURIX TC275. In: 10th European Congress on Embedded Real Time Software and Systems (ERTS 2020), January 2020
Ungerer, T., et al.: Merasa: multicore execution of hard real-time applications supporting analyzability. IEEE Micro 30(5), 66–75 (2010)
Wenzel, I., Kirner, R., Puschner, P.P., Rieder, B.: Principles of timing anomalies in superscalar processors. In: International Conference on Quality Software (QSIC 2005), Melbourne, Australia, pp. 295–306, September 2005
Wilhelm, S., Wachter, B.: Towards symbolic state traversal for efficient WCET analysis of abstract pipeline and cache models. In: 7th International Workshop on Worst-Case Execution Time (WCET) Analysis, Pisa, Italy, 3 July 2007 (2007)
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Binder, B., Asavoae, M., Brandner, F., Ben Hedia, B., Jan, M. (2020). Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture. In: ter Beek, M.H., Ničković, D. (eds) Formal Methods for Industrial Critical Systems. FMICS 2020. Lecture Notes in Computer Science(), vol 12327. Springer, Cham. https://doi.org/10.1007/978-3-030-58298-2_6
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