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Robust Controller Synthesis for Duration Calculus

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Automated Technology for Verification and Analysis (ATVA 2020)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 12302))

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Abstract

In automatic control synthesis, we may need to handle specifications with timing constraints and control such that the system meets the specification as much as possible, which is called robust control. In this paper, we present a method for open loop robust controller synthesis from duration calculus (DC) specifications. For robust synthesis, we propose an approach to evaluate the robustness of DC specifications on a given run of a system. We leverage a CEGIS like method for synthesizing robust control signals. In our method, the DC specifications and the system under control are encoded into mixed integer linear problems, and the optimization problem is solved to yield a control signal. We have implemented a tool (ControlDC) based on the method and applied it on a set of benchmarks.

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Notes

  1. 1.

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  2. 2.

    Traditionally denoted as \(\frown \).

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Authors and Affiliations

  1. Department of Computer Science and Engineering, IIT Bombay, Mumbai, India

    Kalyani Dole, Ashutosh Gupta & Shankara Narayanan Krishna

Authors
  1. Kalyani Dole
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  2. Ashutosh Gupta
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  3. Shankara Narayanan Krishna
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Corresponding author

Correspondence to Kalyani Dole .

Editor information

Editors and Affiliations

  1. Vietnam National University (VNU-UET), Hanoi, Vietnam

    Dang Van Hung

  2. University of Pennsylvania, Philadelphia, PA, USA

    Oleg Sokolsky

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Dole, K., Gupta, A., Krishna, S.N. (2020). Robust Controller Synthesis for Duration Calculus. In: Hung, D.V., Sokolsky, O. (eds) Automated Technology for Verification and Analysis. ATVA 2020. Lecture Notes in Computer Science(), vol 12302. Springer, Cham. https://doi.org/10.1007/978-3-030-59152-6_24

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  • DOI: https://doi.org/10.1007/978-3-030-59152-6_24

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-59151-9

  • Online ISBN: 978-3-030-59152-6

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