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International Conference on Algorithms and Architectures for Parallel Processing

ICA3PP 2020: Algorithms and Architectures for Parallel Processing pp 92–111Cite as

PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 12452))

Abstract

The problem of high power consumption has become one of the main obstacles that affect the reliability, stability, and performance of high-performance computers. How to get the power of CPU and memory instantaneously and accurately is an important basis for evaluating their power’s optimization methods. At present, much work has been done to model CPU and memory power using the performance monitoring counter (PMC). Most of these models are static, which fit and estimate the power of the corresponding CPU or memory by collecting and counting key performance monitoring events. However, when the performance behavior of the application changes dramatically with time, the accuracy of the real-time power measurement values will decline, because the performance monitoring values used in the power model can not fit the power values well in a long time. In order to solve this problem, we first analyze the changing features of application performance indicators when CPU or memory power changes, especially the correlation between PMC events and CPU and memory power, and then propose a dynamic adaptive power modeling method (DAPM) based on PMC events using dynamic adaptive technology, which is used for real-time power measurement of CPU and memory. The DAPM can realize the adaptive selection/matching of the model by introducing the power measurement data at the node level, and enhance the real-time power measurement accuracy by dynamically expanding the model library. Besides, the running cost of the DAPM is low. Compared with other PMC power models, DAPM can achieve lower CPU and DRAM power error rates. The error rates of three conventional PMC power models are Isci’s model 7%(CPU), Singh’s 7.2%(CPU), and Bircher’s 6.7%(CPU) and 8.8%(DRAM), while the CPU error rate of DAPM is less than 2%, and the DRAM error rate is less than 5.5%.

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Acknowledgements

This work is supported in part by the Advanced Research Project of China under grant number 31511010203 and the Research Program of NUDT grant number ZK18-03-10.

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Authors and Affiliations

  1. National University of Defense Technology, Changsha, Hunan, China

    Yunfang Zhang, Yong Dong, Juan Chen, Zhixin Ou & Yuan Yuan

Authors
  1. Yunfang Zhang
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  2. Yong Dong
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  3. Juan Chen
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  4. Zhixin Ou
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  5. Yuan Yuan
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Corresponding author

Correspondence to Yunfang Zhang .

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Editors and Affiliations

  1. Columbia University, New York, NY, USA

    Meikang Qiu

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Zhang, Y., Dong, Y., Chen, J., Ou, Z., Yuan, Y. (2020). PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling. In: Qiu, M. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2020. Lecture Notes in Computer Science(), vol 12452. Springer, Cham. https://doi.org/10.1007/978-3-030-60245-1_7

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