Abstract
Cache side-channel attacks have become a significant security threat across a variety of hardware architectures. By observing which sets of a cache are accessed by the victim, the attacker gleans critical information about the address bits in the victim’s access, thereby revealing portions of secret keys used by encryption algorithms (or other sensitive information). Fundamentally, this ability to deduce information about addresses given the accessed sets depends on knowing (or discovering) how addresses are mapped to cache sets by hardware.
In this work, we evaluate the security of the various cache mapping functions. Using an information-theoretic formulation, our framework (denoted CHASM) estimates the number of address bits that are likely leaked by different mapping schemes. Our analysis leads to several new insights. One, all one-to-one schemes that map n set-index address bits to \(2^n\) set-indices leak all n bits. Two, based on memory footprint, programs often leak several additional (viz., tag) bits (e.g., AES leaks 39 bits out of 42 at L2). Three, tag bits leak even with the use of address space layout randomization (16–33 bits). Four, the use of huge pages in order to reduce pressure on TLBs increases leakage (5 additional bits on average). Since many of these techniques have opposing impact on performance and security, we use a new security-delay ratio metric to jointly evaluate mapping schemes for both performance and security.
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Notes
- 1.
In this paper we do not directly address attacks based on speculative execution or techniques to mitigate them.
- 2.
Partitioning techniques do not prevent certain types of attacks [35].
- 3.
- 4.
For small bit counts, a table lookup can be used.
- 5.
In the original work, this scheme was applied to the shared L3 cache.
- 6.
In our case, leakage in bit i would depend on all other 40–50 bits requiring \(2^{40}-2^{50}\) probabilities to be estimated.
- 7.
We stop at \(a_6\) as bits \(a_0\) through \(a_5\) are block offset bits that have no impact on cache mapping. In this paper we assume 64-byte cache blocks.
- 8.
As stated previously, we assume a 64-byte cache line size, and 48-bit addresses.
- 9.
SPEC and Cryptography workloads exhibit similar trends and for brevity, we omit their details here.
- 10.
For lack of space, we omitted the Rotate-3 scheme as its leakage is exactly the same as that of Modulo.
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Mosquera, F., Gulur, N., Kavi, K., Mehta, G., Sun, H. (2020). CHASM: Security Evaluation of Cache Mapping Schemes. In: Orailoglu, A., Jung, M., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2020. Lecture Notes in Computer Science(), vol 12471. Springer, Cham. https://doi.org/10.1007/978-3-030-60939-9_17
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