Abstract
The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM models often become the bottleneck for the overall simulation speed. A promising alternative are DRAM simulation models based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. DRAMSys4.0 includes a novel simulator architecture that enables a fast adaptation to new DRAM standards using a Domain Specific Language. We present optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy. Finally, we provide a detailed survey and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.
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Notes
- 1.
- 2.
DRAMSys without a version number refers both to DRAMSys3.0 and DRAMSys4.0.
- 3.
The TLM-AT base protocol consists of the phases BEGIN_REQ, END_REQ, BEGIN_RESP and END_RESP.
- 4.
Timing dependencies are temporal constraints that must be satisfied between issued DRAM commands.
- 5.
Controllers that implement the open-page policy keep the corresponding row open after a read or write access, while controllers that implement the closed-page policy automatically precharge the corresponding row after a read or write access.
- 6.
- 7.
We will report the missing timing dependencies to the developers of the other simulators.
- 8.
Using read snooping a read request can be served directly within the controller if an earlier write request to the same address is still pending.
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Acknowledgements
This work was supported within the Fraunhofer and DFG cooperation programme (Grant no. WE2442/14-1) and supported by the Fraunhofer High Performance Center for Simulation- and Software-based Innovation. Furthermore, we thank Synopsys and the anonymous reviewers for their support.
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Steiner, L., Jung, M., Prado, F.S., Bykov, K., Wehn, N. (2020). DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator. In: Orailoglu, A., Jung, M., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2020. Lecture Notes in Computer Science(), vol 12471. Springer, Cham. https://doi.org/10.1007/978-3-030-60939-9_8
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