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Lock and Fence When Needed: State Space Exploration + Static Analysis = Improved Fence and Lock Insertion

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Integrated Formal Methods (IFM 2020)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 12546))

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Abstract

When targeting modern parallel hardware architectures, constructing correct and high-performing software is complex and time-consuming. In particular, reorderings of memory accesses that violate intended sequentially consistent behaviour are a major source of bugs. Applying synchronisation mechanisms to repair these should be done sparingly, as they negatively impact performance.

In the past, both static analysis approaches and techniques based on explicit-state model checking have been proposed to identify where synchronisation fences have to be placed in a program. The former are fast, but the latter more precise, as they tend to insert fewer fences. Unfortunately, the model checking techniques suffer a form of state space explosion that is even worse than the traditional one.

In this work, we propose a technique using a combination of state space exploration and static analysis. This combination is in terms of precision comparable to purely model checking-based techniques, but it reduces the state space explosion problem to the one typically seen in model checking. Furthermore, experiments show that the combination frequently outperforms both purely model checking and static analysis techniques. In addition, we have added the capability to check for atomicity violations, which is another major source of bugs.

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Notes

  1. 1.

    In order for this analysis to terminate, it is important that the system is finite-state, or at least has a finite-state quotient that can be derived prior to state space generation [32]. It may perform infinite executions, though, i.e., have cyclic behaviour between its states.

  2. 2.

    We use the term ’delay’ here to refer to the remedy for non-SC behaviour [36], and not, as for instance later done in [4, 6, 7], to refer to the problem, i.e., the unsafe behaviour itself.

  3. 3.

    We ignore rdw and detour dependencies between threads under ARMv7/POWER [7], since those cannot be checked thread-locally. The penalty is that we under-approximate the guarantees of those memory models, but the effect seems marginal, as experimentally observed in [7].

  4. 4.

    Note that we define state spaces by means of Labelled Transition Systems, in which transitions are labelled with events. However, the technique we propose in this paper can be adapted to Kripke structures, by encoding via state predicates the events that are performed.

  5. 5.

    A proof can be found at http://www.win.tue.nl/~awijs/seqcon-analyser.

  6. 6.

    A proof sketch can be found at http://www.win.tue.nl/~awijs/seqcon-analyser.

  7. 7.

    See http://www.win.tue.nl/~awijs/seqcon-analyser for the models and our tool.

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Authors and Affiliations

  1. Eindhoven University of Technology, Eindhoven, The Netherlands

    Sander de Putter & Anton Wijs

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  1. Sander de Putter
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Correspondence to Anton Wijs .

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  1. University of Surrey, Guildford, UK

    Brijesh Dongol

  2. Royal Institute of Technology - KTH, Stockholm, Sweden

    Elena Troubitsyna

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de Putter, S., Wijs, A. (2020). Lock and Fence When Needed: State Space Exploration + Static Analysis = Improved Fence and Lock Insertion. In: Dongol, B., Troubitsyna, E. (eds) Integrated Formal Methods. IFM 2020. Lecture Notes in Computer Science(), vol 12546. Springer, Cham. https://doi.org/10.1007/978-3-030-63461-2_16

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  • DOI: https://doi.org/10.1007/978-3-030-63461-2_16

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