Abstract
Clustering is the process of distributing synthesized and packed circuits into Field Programmable Gate Array (FPGA) clusters effectively. Clustering is a crucial phase of FPGA Computer-Aided Design (CAD) flow since it majorly interferes afterwards in the quality and performance of the placed and routed circuit in terms of power, area and delay. It is mainly controlled by hardware constraints of specific target architectures. In this paper, we propose Adapted Multilevel Partitioner (A-Part) as a clustering algorithm targeting Mesh of Clusters (MoCs) FPGA. We explore the impact of A-Part on MoCs FPGA performance compared to T-VPack. This paper shows through experimentation that A-Part ameliorates power consumption, area and critical path delay by an average of 7%, 5% and 11% respectively compared to T-VPack for MoCs FPGA.
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Bouaziz, K., Chtourou, S., Marrakchi, Z., Obeid, A.M., Abid, M. (2021). A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGA. In: Abraham, A., Piuri, V., Gandhi, N., Siarry, P., Kaklauskas, A., Madureira, A. (eds) Intelligent Systems Design and Applications. ISDA 2020. Advances in Intelligent Systems and Computing, vol 1351. Springer, Cham. https://doi.org/10.1007/978-3-030-71187-0_39
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DOI: https://doi.org/10.1007/978-3-030-71187-0_39
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