Abstract
Hardware simulation is always a compromise between the speed of the simulator and the accuracy of the estimated runtime on the real hardware. Instrumenting fast simulation frameworks to estimate runtimes always results in tremendous slow-downs. In this paper, a quantization is done regarding the minimal overhead that can be expected when adding architectural models to a fast JIT enhanced emulation. Previous work is only focused on new approaches and improving available methods, but not on the unavoidable overhead that is introduced with any kind of instrumentation. Thus, the additional simulation time of calling an empty stub function instead of a fully implemented architectural model is investigated. We show relative runtimes for calling a function after executing each instruction and after executing a block of instructions. Also, a comparison against fully implemented models is done. On the test platforms, an academic and a commercial processor simulator were evaluated. The resulting average relative runtimes of the minimal introduced overhead are determined to be between 2.24 and 8.09 meaning that an emulation takes twice to eight times as long with instrumentation enabled.
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In git commit 68d8ef4ec540682c3538d4963e836e43a211dd17.
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Rachuj, S., Fey, D., Reichenbach, M. (2021). Impact of Performance Estimation on Fast Processor Simulators. In: Song, H., Jiang, D. (eds) Simulation Tools and Techniques. SIMUtools 2020. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 370. Springer, Cham. https://doi.org/10.1007/978-3-030-72795-6_7
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