Abstract
Programmable Data Planes is a novel paradigm that enables efficient offloading of network applications. An important enabler for this paradigm is the current available SmartNICs, which should satisfy rigid network requirements such as high throughput and low latency. Despite recent research in this field, not much attention was given to understand the costs and limitations of offloading network applications into SmartNIC devices. Existing offloading approaches either neglect the existing limitations of SmartNICs or assume that as a fixed cost – leading, therefore, to sub-optimal offloading approaches. In this work, we conduct a comprehensive evaluation of SmartNICs in order to quantify existing performance limitations. We provide insights on network performance metrics such as throughput and packet latency while considering different key building blocks of complex P4 programs (e.g., registers, cryptography functions, or packet recirculation). Results show that line-rate throughput can degrade up to 8x, while latency can increase as much as 80x when performing memory-intensive operations in the data plane.
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Acknowledgements
This work was partially funded by National Council for Scientific and Technological Development (CNPq) (grant 427814/2018-9), São Paulo Research Foundation (FAPESP) (grant 2018/23092-1), Rio Grande do Sul Research Foundation (FAPERGS) (grants 19/2551-0001266-7,20/2551-000483-0, 19/2551-0001224-1).
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Viegas, P.B., de Castro, A.G., Lorenzon, A.F., Rossi, F.D., Luizelli, M.C. (2021). The Actual Cost of Programmable SmartNICs: Diving into the Existing Limits. In: Barolli, L., Woungang, I., Enokido, T. (eds) Advanced Information Networking and Applications. AINA 2021. Lecture Notes in Networks and Systems, vol 225. Springer, Cham. https://doi.org/10.1007/978-3-030-75100-5_17
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