Abstract
Today, the need for real-time analytics and faster decision making mechanisms has led to the adoption of hardware accelerators, such as GPUs and FPGAs, within the edge-cloud computing continuum. Moreover, the need for energy-, yet performance-efficient solutions both in the edge and cloud has led to the rise of approximate computing as a promising paradigm, where “acceptable errors” are introduced to error-tolerant applications, thus, providing significant power-saving gains. In this work, we leverage approximate computing for exploiting performance-energy trade-offs of FPGA accelerated kernels with faster design time though an extended source-to-source HLS compiler based on Xilinx Vitis framework. We introduce a novel programming interface that operates at a high level of abstraction, thus, enabling automatic optimizations to the existing HLS design flow supporting both embedded and cloud devices through a common API. We evaluate our approach over three different application from DSP and machine learning domains and show that a decrease of 27% and 28% in power consumption, 61% and 69% in DSP utilization and 7% in clock period is achieved for Alveo U200 and ZCU104 FPGA platforms, on average.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Xilinx. https://www.xilinx.com/
Barroso, L.A., Hölzle, U.: The case for energy-proportional computing. Computer 40(12), 33–37 (2007)
Chippa, V.K., Chakradhar, S.T., Roy, K., Raghunathan, A.: Analysis and characterization of inherent application resilience for approximate computing. In: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–9 (2013). https://doi.org/10.1145/2463209.2488873
Danopoulos, D., Kachris, C., Soudris, D.: A quantitative comparison for image recognition on accelerated heterogeneous cloud infrastructures, pp. 171–189 (September 2019). https://doi.org/10.1201/9780429399602-8
Danopoulos, D., Kachris, C., Soudris, D.: Utilizing cloud FPGAs towards the open neural network standard. Sustain. Comput.: Inform. Syst. 30, 100520 (2021)
Finnerty, A., Ratigner, H.: Reduce power and cost by converting from floating point to fixed point. WP491 (v1. 0) (2017)
Guan, Y., et al.: FP-DNN: an automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates. In: 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 152–159 (2017). https://doi.org/10.1109/FCCM.2017.25
Guo, K., et al.: Angel-eye: a complete design flow for mapping CNN onto customized hardware. In: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 24–29 (2016). https://doi.org/10.1109/ISVLSI.2016.129
Homsirikamol, E., George, K.G.: Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: the Caesar contest case study. In: 2017 International Conference on Field Programmable Technology (ICFPT), pp. 120–127 (2017). https://doi.org/10.1109/FPT.2017.8280129
Ko, J.H., Fromm, J., Philipose, M., Tashev, I., Zarar, S.: Precision scaling of neural networks for efficient audio processing. arXiv preprint arXiv:1712.01340 (2017)
Nane, R., et al.: A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35, 1591–1604 (2015). https://doi.org/10.1109/TCAD.2015.2513673
Saadat, H., Bokhari, H., Parameswaran, S.: Minimally biased multipliers for approximate integer and floating-point multiplication. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 37(11), 2623–2635 (2018)
Sharma, H., et al.: Bit fusion: bit-level dynamically composable architecture for accelerating deep neural network. In: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp. 764–775 (2018)
Shawahna, A., Sait, S.M., El-Maleh, A.: FPGA-based accelerators of deep learning networks for learning and classification: a review. IEEE Access 7, 7823–7859 (2019). https://doi.org/10.1109/ACCESS.2018.2890150
Shi, W., Cao, J., Zhang, Q., Li, Y., Xu, L.: Edge computing: vision and challenges. IEEE Internet Things J. 3(5), 637–646 (2016)
Wess, M., Manoj, P.D.S., Jantsch, A.: Neural network based ECG anomaly detection on FPGA and trade-off analysis, pp. 1–4 (May 2017). https://doi.org/10.1109/ISCAS.2017.8050805
Acknowledgment
This work has been supported by the E.C. funded program SERRANO under H2020 Grant Agreement No: 101017168.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Kokkinis, A., Ferikoglou, A., Danopoulos, D., Masouros, D., Siozios, K. (2021). Leveraging HW Approximation for Exploiting Performance-Energy Trade-offs Within the Edge-Cloud Computing Continuum. In: Jagode, H., Anzt, H., Ltaief, H., Luszczek, P. (eds) High Performance Computing. ISC High Performance 2021. Lecture Notes in Computer Science(), vol 12761. Springer, Cham. https://doi.org/10.1007/978-3-030-90539-2_27
Download citation
DOI: https://doi.org/10.1007/978-3-030-90539-2_27
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-90538-5
Online ISBN: 978-3-030-90539-2
eBook Packages: Computer ScienceComputer Science (R0)