Abstract
RISC-V is a new instruction set architecture (ISA) that has emerged in recent years. Compared with previous computer instruction architectures, RISC-V has outstanding features such as simple instructions, modular instruction set and supporting agile development. Due to these advantages, a large number of chips have been designed based on RISC-V ISA. However, compared with other ISAs, the efficiency or performance of RISC-V architecture is still not clear. In this paper, we investigate the performance difference of three mainstream RISC processor systems (i.e., ARM, MIPS and RISC-V). We use two open source benchmark tools-UnixBench and LMbench, to widely evaluate the processor performance, such as computing efficiency, read and write file delay, local communication bandwidth, etc. A total of 19 detailed performance tests on these three ISA systems are carried out. The testing results show: i) MIPS achieves the highest scores and shortest context switching delay whether it has a large number of file copying or pipeline communication; ii) RISC-V has high local communication bandwidth and strong scientific computing capabilities, but has highest communication and file access delays; iii) ARM’s local communication bandwidth is low, and the delay in all aspects is slightly higher than that of MIPS.
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Acknowledgment
This work is supported by Key-Area Research and Development Program of Guangdong Province (NO. 2020B010164003), National Natural Science Foundation of China (No. 62072451), Shenzhen Basic Research Program (No. JCYJ20200109115418592), Science and Technology Development Fund of Macao S.A.R (FDCT) under number 0015/2019/AKP, and Youth Innovation Promotion Association CAS (NO. 2019349).
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Liu, Y., Ye, K., Xu, CZ. (2022). Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V. In: Ye, K., Zhang, LJ. (eds) Cloud Computing – CLOUD 2021. CLOUD 2021. Lecture Notes in Computer Science(), vol 12989. Springer, Cham. https://doi.org/10.1007/978-3-030-96326-2_5
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