Abstract
Many emerging nanotechnologies extensively assemble circuits based on the voter-based majority logic (ML). In this chapter, we aim to provide a comprehensive investigation of approximate unsigned and signed multiplier designs based on ML. Approximate partial product generation, reduction, and compression are discussed, specifically with some complementary strategies guided by an analysis of error effects to compensate for the accuracy loss. The approximate multiplier designs are comparatively evaluated from error and circuit characteristics. Image processing and neural networks as case studies of error-tolerant applications are presented to show the validity and advantages of the proposed designs.
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Acknowledgements
This work was supported by the Natural Sciences and Engineering Research Council (NSERC) of Canada (Project Number: RES0048688). T. Zhang is supported by a PhD scholarship from the China Scholarship Council (CSC).
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Zhang, T. et al. (2022). Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications. In: Liu, W., Lombardi, F. (eds) Approximate Computing. Springer, Cham. https://doi.org/10.1007/978-3-030-98347-5_6
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DOI: https://doi.org/10.1007/978-3-030-98347-5_6
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