Abstract
In this paper, we present a new approach for mapping LLVM IR to binary machine code for overcoming the current limitations of host-based simulations of performance-critical embedded software imposed by compiler optimizations. Our novel, fully automated mapping approach even copes with aggressive compiler optimizations without requiring any modification to the compiler or the need of expert supervision. Experimental results show that accurate mappings are produced even when compiling with the highest level of optimization (average error below 2%). The proposed simulation methodology provides a speedup of at least 26 compared to the widely used gem5 simulator.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Aho, A., et al.: Compilers: Principles, Techniques and Tools, 2nd edn. Addison-Wesley, Boston (2007)
Becker, M., Pazaj, M., Chakraborty, S.: WCET analysis meets virtual prototyping: improving source-level timing annotations. In: 22nd International Workshop on Software and Compilers for Embedded Systems (2019)
Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News (2011)
Butko, A., Garibotti, R., Ost, L., Sassatelli, G.: Accuracy evaluation of gem5 simulator system. In: International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE (2012)
Chakravarty, S., Zhao, Z., Gerstlauer, A.: Automated, retargetable back-annotation for host compiled performance and power modeling. In: International Conference on HW/SW Codesign and System Synthesis. IEEE (2013)
Cornaglia, A., Hasan, M.S., Viehl, A., Bringmann, O., Rosenstiel, W.: JIT-based context-sensitive timing simulation for efficient platform exploration. In: 25th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE (2020)
Gustafsson, J., Betts, A., Ermedahl, A., Lisper, B.: The Mälardalen WCET benchmarks: past, present and future. In: 10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010) (2010)
Jahić, J., Kuhn, T., Jung, M., Wehn, N.: BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level. In: 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (2018)
Lattner, C., Adve, V.: LLVM: A compilation framework for lifelong program analysis and transformation. In: International Symposium on Code Generation and Optimization. IEEE (2004)
Lowe-Power, J., Ahmad, A.M., Akram, A., Alian, M., et al.: The gem5 simulator: Version 20.0+. arXiv preprint arXiv:2007.03152 (2020)
Lu, K., Müller-Gritschneder, D., Schlichtmann, U.: Hierarchical control flow matching for source-level simulation of embedded software. In: 2012 International Symposium on System on Chip (SoC). IEEE (2012)
Matoussi, O., Pétrot, F.: A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation. In: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE (2018)
Stattelmann, S., Bringmann, O., Rosenstiel, W.: Dominator homomorphism based code matching for source-level simulation of embedded software. In: International Conference on HW/SW Codesign and System Synthesis (2011)
The LLVM Compiler Infrastructure: Machine IR (MIR) Format Reference Manual. https://llvm.org/docs/MIRLangRef.html
The LLVM Compiler Infrastructure: The LLVM Target-Independent Code Generator. https://llvm.org/docs/CodeGenerator.html
Wang, Z., Henkel, J.: Accurate source-level simulation of embedded software with respect to compiler optimizations. In: Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE (2012)
Wang, Z., Herkersdorf, A.: An efficient approach for system-level timing simulation of compiler-optimized embedded software. In: 46th Design Automation Conference (DAC). IEEE (2009)
Acknowledgements
This work has been partially supported by the German Federal Ministry of Education and Research (BMBF) within the projects COMAPCT under grant 01\(\mid \)S17028C and progressivKI under grant 19A21006M.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 Springer Nature Switzerland AG
About this paper
Cite this paper
Cornaglia, A., Viehl, A., Bringmann, O. (2022). Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded Software. In: Orailoglu, A., Jung, M., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science, vol 13227. Springer, Cham. https://doi.org/10.1007/978-3-031-04580-6_1
Download citation
DOI: https://doi.org/10.1007/978-3-031-04580-6_1
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-04579-0
Online ISBN: 978-3-031-04580-6
eBook Packages: Computer ScienceComputer Science (R0)