Skip to main content

A Proposal for FPGA-Accelerated Deep Learning Ensembles in MPSoC Platforms Applied to Malware Detection

  • Conference paper
  • First Online:
Quality of Information and Communications Technology (QUATIC 2022)

Abstract

Ensembles of Deep Neural Networks can be profitably employed to improve the overall network performance in a range of applications, including for example online malware detection performed by edge computing systems. In such edge applications, which are often dominated by inference operations, FPGA-based MPSoC platforms may play a competitive role compared to GPU devices because of higher energy efficiency. Furthermore, their hardware reconfiguration capabilities offer a perfect match with the requirement of model diversity posed by Ensemble Learning. This exploratory short paper presents a research plan towards an FPGA-based MPSoC platform exploiting dynamic partial reconfiguration in edge systems for accelerating Deep Learning Ensembles. We present the background and the main rationale behind our envisioned architecture. We also present a preliminary security analysis discussing possible threats and vulnerabilities along with the mitigations enabled by the architecture we plan to develop.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 69.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html.

  2. 2.

    https://www.kernel.org/doc/html/v4.19/driver-api/fpga/fpga-mgr.html.

References

  1. Abdelsalam, M., Krishnan, R., Huang, Y., Sandhu, R.: Malware detection in cloud infrastructures using convolutional neural networks. In: 2018 IEEE 11th International Conference on Cloud Computing (CLOUD), pp. 162–169. IEEE (2018)

    Google Scholar 

  2. Alhalabi, B., Gaber, M.M., Basura, S.: MicroNets: a multi-phase pruning pipeline to deep ensemble learning in IoT devices. Comput. Electr. Eng. 96, 107581 (2021)

    Google Scholar 

  3. Azmandian, F., Moffie, M., Alshawabkeh, M., Dy, J., Aslam, J., Kaeli, D.: Virtual machine monitor-based lightweight intrusion detection. ACM SIGOPS Oper. Syst. Rev. 45(2), 38–53 (2011)

    Google Scholar 

  4. Blaiech, A.G., Khalifa, K.B., Valderrama, C., Fernandes, M.A., Bedoui, M.H.: A survey and taxonomy of FPGA-based deep learning accelerators. J. Syst. Architect. 98, 331–345 (2019)

    Article  Google Scholar 

  5. Chen, Y.H., Krishna, T., Emer, J.S., Sze, V.: Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-State Circuits 52(1), 127–138 (2017). https://doi.org/10.1109/JSSC.2016.2616357

  6. Courbariaux, M., Hubara, I., Soudry, D., El-Yaniv, R., Bengio, Y.: Binarized neural networks: training deep neural networks with weights and activations constrained to +1 or \(-\)1 (2016). https://doi.org/10.48550/ARXIV.1602.02830

  7. Farhadi, M., Ghasemi, M., Yang, Y.: A novel design of adaptive and hierarchical convolutional neural networks using partial reconfiguration on FPGA. In: 2019 IEEE High Performance Extreme Computing Conference (HPEC), pp. 1–7 (2019). https://doi.org/10.1109/HPEC.2019.8916237

  8. Garfinkel, T., Rosenblum, M., et al.: A virtual machine introspection based architecture for intrusion detection. In: NDSS, vol. 3, pp. 191–206. Citeseer (2003)

    Google Scholar 

  9. Geman, S., Bienenstock, E., Doursat, R.: Neural networks and the bias/variance dilemma. Neural Comput. 4(1), 1–58 (1992)

    Article  Google Scholar 

  10. Guan, Y., Yuan, Z., Sun, G., Cong, J.: FPGA-based accelerator for long short-term memory recurrent neural networks. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 629–634 (2017). https://doi.org/10.1109/ASPDAC.2017.7858394

  11. Hebbal, Y., Laniepce, S., Menaud, J.M.: Virtual machine introspection: techniques and applications. In: 2015 10th International Conference on Availability, Reliability and Security, pp. 676–685. IEEE (2015)

    Google Scholar 

  12. Intel®: Intel® Architecture Instruction Set Extensions and Future Features (2021)

    Google Scholar 

  13. Kalash, M., Rochan, M., Mohammed, N., Bruce, N.D., Wang, Y., Iqbal, F.: Malware classification with deep convolutional neural networks. In: 2018 9th IFIP International Conference on New Technologies, Mobility and Security (NTMS), pp. 1–5. IEEE (2018)

    Google Scholar 

  14. Nataraj, L., Karthikeyan, S., Jacob, G., Manjunath, B.S.: Malware images: visualization and automatic classification. In: Proceedings of the 8th International Symposium on Visualization for Cyber Security, pp. 1–7 (2011)

    Google Scholar 

  15. Pinneterre, S., Chiotakis, S., Paolino, M., Raho, D.: vFPGAmanager: a virtualization framework for orchestrated FPGA accelerator sharing in 5G cloud environments. In: 2018 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), pp. 1–5 (2018). https://doi.org/10.1109/BMSB.2018.8436930

  16. Saharkhizan, M., Azmoodeh, A., Dehghantanha, A., Choo, K.K.R., Parizi, R.M.: An ensemble of deep recurrent neural networks for detecting IoT cyber attacks using network traffic. IEEE Internet Things J. 7(9), 8852–8859 (2020)

    Article  Google Scholar 

  17. Sang, D.V., Cuong, D.M., Cuong, L.T.B.: An effective ensemble deep learning framework for malware detection. In: Proceedings of the Ninth International Symposium on Information and Communication Technology, pp. 192–199 (2018)

    Google Scholar 

  18. Seyoum, B., Pagani, M., Biondi, A., Balleri, S., Buttazzo, G.: Spatio-temporal optimization of deep neural networks for reconfigurable FPGA SoCs. IEEE Trans. Comput. 70(11), 1988–2000 (2021). https://doi.org/10.1109/TC.2020.3033730

  19. Shi, W., Cao, J., Zhang, Q., Li, Y., Xu, L.: Edge computing: vision and challenges. IEEE Internet Things J. 3(5), 637–646 (2016)

    Google Scholar 

  20. Umuroglu, Y., et al.: FINN: a framework for fast, scalable binarized neural network inference. In: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, February 2017. https://doi.org/10.1145/3020078.3021744

  21. Vanerio, J., Casas, P.: Ensemble-learning approaches for network security and anomaly detection. In: Proceedings of the Workshop on Big Data Analytics and Machine Learning for Data Communication Networks, pp. 1–6 (2017)

    Google Scholar 

  22. Vu, D.V., Sander, O., Sandmann, T., Baehr, S., Heidelberger, J., Becker, J.: Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization. In: 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), pp. 1–6 (2014). https://doi.org/10.1109/ReConFig.2014.7032516

  23. Xiao, Y., Xing, C., Zhang, T., Zhao, Z.: An intrusion detection model based on feature reduction and convolutional neural networks. IEEE Access 7, 42210–42219 (2019)

    Article  Google Scholar 

  24. Yan, J., Qi, Y., Rao, Q.: Detecting malware with an ensemble method based on deep neural network. Secur. Commun. Netw. 2018, 1–16 (2018)

    Google Scholar 

  25. Yao, W., Zhang, K., Yu, C., Zhao, H.: Exploiting ensemble learning for edge-assisted anomaly detection scheme in e-healthcare system. In: 2021 IEEE Global Communications Conference (GLOBECOM), pp. 1–7. IEEE (2021)

    Google Scholar 

Download references

Acknowledgements

This work was partly founded by the PON “Ricerca e Innovazione” 2014–2020, Azione IV.5, Ministerial Decree n. 1061 of the Italian Ministry of University and Research.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Vincenzo Maisto .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2022 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Cilardo, A., Maisto, V., Mazzocca, N., Rocco di Torrepadula, F. (2022). A Proposal for FPGA-Accelerated Deep Learning Ensembles in MPSoC Platforms Applied to Malware Detection. In: Vallecillo, A., Visser, J., Pérez-Castillo, R. (eds) Quality of Information and Communications Technology. QUATIC 2022. Communications in Computer and Information Science, vol 1621. Springer, Cham. https://doi.org/10.1007/978-3-031-14179-9_16

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-14179-9_16

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-14178-2

  • Online ISBN: 978-3-031-14179-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics