EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis

Abstract

High-Level Synthesis (HLS) has become increasingly popular for FPGA accelerators. Its main benefit is the considerably simpler development and faster time-to-market than traditional RTL designs. HLS also allows developers with less in-depth hardware design knowledge to employ FPGA accelerators for their applications. However, like traditional CPUs, these designs often suffer from an insufficient memory bandwidth to provide data to all computational units. High-Bandwidth Memory (HBM) has been developed and recently added to commercial FPGAs to overcome the limited bandwidth. As stacked DRAM, it achieves a substantially higher bandwidth than traditional DRAM through its high number of independent memory channels. However, current HLS tools do not fully take this characteristic into account. They generate accelerators that either do not automatically use all available channels for HBM access and thus lose performance or require more complex manual data partitioning and replication schemes between the channels. That leads to failure to meet the expected gains of application developers. Therefore, in this paper, we propose an utterly application-independent way to efficiently handle HBM as a unified pool of memory in an HLS tool in a generic manner. It keeps the advantage of high bandwidth for many applications while hiding the multi-channel complexity from the developer’s HLS accelerator description. That enables the design of HLS cores that run efficiently on FPGAs without deep consideration of the available memory.