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IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip

VLSI-SoC 2021: VLSI-SoC: Technology Advancement on SoC Design pp 175–203Cite as

END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator

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Part of the book series: IFIP Advances in Information and Communication Technology ((IFIPAICT,volume 661))

Abstract

True Random Number Generators (TRNGs) are essential primitives in any cryptographic system. They provide the foundation to secure authorization and authentication. This work proposes a generator that exploits the metastability effect of cross-coupled logic gates, as found in SR latches. Based on emerging reconfigurable transistor technology, a random number generator design has been proposed that doubles the throughput, compared to a similar standard CMOS design, by exploiting transistor-level reconfiguration. The proposed design is superior in terms of the number of transistors per block, power consumption and in critical path delay with respect to its CMOS counterpart. Random Number bit sequence are generated by operating the given design at three operating frequencies of 10 MHz, 100 MHz and 200 MHz. Firstly, the Shannon entropy for the generated bit sequence is measured, and then the generated bit sequence are subjected to statistical evaluation using the NIST benchmark suite. The \(P^\prime \) values for the NIST benchmarks is above the accepted threshold, which underlines the assumption that the designed circuit produces the random numbers based on the metastability effect.

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Notes

  1. 1.

    This is because the remaining benchmarks in the suite (Maurer’s Universal statistical, Linear, Radom excursion tests) require more than \(10^7\) bits for evaluation and it would amount to an unfeasible time duration to generate the bits using simulation [40] for a TCAD-based verilog-A model for RFETs [13].

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Authors and Affiliations

  1. Chair of Processor Design, Technische Universität Dresden, Dresden, Germany

    Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza & Akash Kumar

  2. NaMLab gGmbH, Dresden, Germany

    Jens Trommer & Thomas Mikolajick

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  1. Synopsys Chile R&D Center, Vitacura, Chile

    Victor Grimblatt

  2. Nanyang Technological University, Singapore, Singapore

    Chip Hong Chang

  3. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

    Ricardo Reis

  4. Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

  5. Politecnico di Torino, Turin, Italy

    Andrea Calimera

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Rai, S. et al. (2022). END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator. In: Grimblatt, V., Chang, C.H., Reis, R., Chattopadhyay, A., Calimera, A. (eds) VLSI-SoC: Technology Advancement on SoC Design. VLSI-SoC 2021. IFIP Advances in Information and Communication Technology, vol 661. Springer, Cham. https://doi.org/10.1007/978-3-031-16818-5_9

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