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A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier

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VLSI Design and Test (VDAT 2022)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1687))

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Abstract

This article presents the design of a GaN-only robust low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) integrated with a reverse recovery time compensation (RRTC) circuit at the input. We use the \(\mathbf {0.25\,\mu m}\) GaN HEMT process from UMS in the complete design of robust LNA MMIC in the 5.8–6.2 GHz band. The proposed MMIC design is compact and requires a single substrate to fabricate LNA and RRTC circuits. To test the design, we apply a high power RF pulse of 40 dBm for 250 nsec and achieve a 16.8 dB reduction in gain \(S_{21}\) with an RRT limiter circuit in place. The simulated LNA takes less than 100 nsec to get back to its normal operating condition after applying a wideband (4–10 GHz) and high power (10–40 dBm) RF pulse for 250 nsec.

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Acknowledgement

The work was funded in part by the IUSSTF/USISTEF/9th call/EC-059/2018/2019–20, SwarnaJayanti Fellowship under Grant DST/SJF/ETA-02/2017–18 and in part by the FIST Scheme of the Department of Science and Technology under Grant SR/FST/ETII-072/2016.

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Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India

    Neha Bajpai & Yogesh Singh Chauhan

Authors
  1. Neha Bajpai
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  2. Yogesh Singh Chauhan
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Corresponding author

Correspondence to Neha Bajpai .

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Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India

    Ambika Prasad Shah

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India

    Anand Darji

  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India

    Jaynarayan Tudu

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Bajpai, N., Chauhan, Y.S. (2022). A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_19

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  • DOI: https://doi.org/10.1007/978-3-031-21514-8_19

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  • Online ISBN: 978-3-031-21514-8

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