Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound

Abstract

In approximate circuits, the functionality of the circuit is modified to improve non-functional parameters such as area, power, and delay. These circuits are targeted for error-resilient applications like image processing, neural networks, etc. These applications can achieve acceptable output results even after the introduction of approximation in computations. Error computation becomes crucial in these applications and can be done either using simulation or formal approaches. Both these methods of error computation are not scalable for circuits with inputs larger than 32 bits. In this work, we used scalable construction of large array multipliers using smaller formally worst-case error guaranteed array multipliers obtained using an LUT-SAT based approach and guaranteed overall worst-case error bounds analytically. Our 8 $\times$ 8 approximate multipliers based on the LUT-SAT approach have 0.59% less area as compared to the state-of-the-art EvoApprox library-based multipliers. We compared the 16 $\times$ 16 multipliers constructed using four 8 $\times$ 8 LUT-SAT-based multipliers with 16 $\times$ 16 multipliers constructed using four 8 $\times$ 8 Evo multipliers. We have performed the area and various error metric comparisons.

C. K. Jha—The work was carried out when Chandan Kumar Jha was at CADSL, IIT Bombay.