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International Symposium on VLSI Design and Test

VDAT 2022: VLSI Design and Test pp 435–449Cite as

Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees

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Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1687))

Abstract

Approximate computing relaxes accuracy, enhance efficiency, and benefit in terms of area. It is widely popular in emerging applications like mining, search, vision, recognition where inaccuracies are tolerable. This tolerance towards errors is exploited to design circuits. The most crucial stage is to strike the proper balance between error and output quality. A systematic framework is used for generating approximate circuits with a specific error guarantee. The key idea is to use the property checking technique based on SAT to compute the worst-case error. In this design method Look-up Table (LUT) is used to acquire approximation with worst-case error metric as a constraint. A novel technique is proposed to select nodes for insertion of LUTs is discussed. The method evolved around toggle count and observability of nodes in the circuit. The number of transistors used, and errors is examined for analysis. This analysis will help in evaluating the output of the adder circuit obtained through approximation. This method was implemented using Yosys and evaluated adder circuit. The aim of this paper is to adopt formal methods such as satiability solvers for analysis of approximate adder circuits. When the worst-case absolute error and area are taken into account for 64 bit, 32 bit and 16 bit our solution will provide a superior trade-off.

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Acknowledgment

This work is supported by Visvesvaraya Ph.D. Scheme, Meity, Govt. of India. MEITY-PHD-2950.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur, 302017, India

    Pooja Choudhary & Lava Bhargava

  2. Department of Electronics and Communication Engineering, Swami Keshvanand Institute of Technology Management and Gramothan, Jaipur, 302017, India

    Pooja Choudhary

  3. Design and Education Center, VLSI, University of Tokyo, Bunkyo City, Japan

    Masahiro Fujita

  4. Department of Electrical Engineering & Department of Computer Science and Engineering, Indian Institute of Technology, Bombay, 400076, India

    Virendra Singh

Authors
  1. Pooja Choudhary
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  2. Lava Bhargava
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  3. Masahiro Fujita
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  4. Virendra Singh
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Corresponding author

Correspondence to Pooja Choudhary .

Editor information

Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India

    Ambika Prasad Shah

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India

    Anand Darji

  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India

    Jaynarayan Tudu

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Choudhary, P., Bhargava, L., Fujita, M., Singh, V. (2022). Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_36

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  • DOI: https://doi.org/10.1007/978-3-031-21514-8_36

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-21513-1

  • Online ISBN: 978-3-031-21514-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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