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CPU Architecture Modelling and Co-design

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High Performance Computing (ISC High Performance 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 13948))

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Abstract

Co-design has become an established process for both developing high-performance computing (HPC) architectures (and, more specifically, CPU architectures) as well as HPC applications. The co-design process is frequently based on models. This paper discusses an approach to CPU architecture modelling and its relation to modelling theory. The approach is implemented using the gem5 simulator for Arm-based CPU architectures and applied for the purpose of generating co-design knowledge using two applications that are widely used on HPC systems.

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Notes

  1. 1.

    The used simulator source including configuration are available at https://github.com/binebrank/gem5/tree/neoverse_model.

  2. 2.

    https://github.com/ssvb/tinymembench.

  3. 3.

    https://github.com/benchmark-subsetting/NPB3.0-omp-C.

  4. 4.

    In the carbon nanotube use case, 19-point stencil is used in combination with a 7-point stencil, which we have not evaluated.

  5. 5.

    The used source code, together with manually vectorized functions, is available at https://gitlab.jsc.fz-juelich.de/brank1/gpaw-benchmarks.

  6. 6.

    The rename component in gem5 stalls if there are no physical registers available or the ROB is full.

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Acknowledgements

The authors would like to thank the Stony Brook Research Computing and Cyberinfrastructure, and the Furthermore, we want to thank the Open Edge and HPC Initiative for access to an Arm-based development Funding for parts of this work has been received from the European Commission H2020 program under Grant Agreement 779877 (Mont-Blanc 2020), and from the Swedish e-Science Research Centre (SeRC).

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Authors and Affiliations

  1. Microsoft, Munich, Germany

    Bine Brank

  2. Division of Computational Science and Technology, KTH Royal Institute of Technology, Stockholm, Sweden

    Dirk Pleiter

Authors
  1. Bine Brank
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  2. Dirk Pleiter
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Correspondence to Dirk Pleiter .

Editor information

Editors and Affiliations

  1. University of Maryland, College Park, MD, USA

    Abhinav Bhatele

  2. NVIDIA, Helsinki, Finland

    Jeff Hammond

  3. Université Paris-Saclay, Gif-sur-Yvette, France

    Marc Baboulin

  4. CERFACS, Toulouse, France

    Carola Kruse

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Brank, B., Pleiter, D. (2023). CPU Architecture Modelling and Co-design. In: Bhatele, A., Hammond, J., Baboulin, M., Kruse, C. (eds) High Performance Computing. ISC High Performance 2023. Lecture Notes in Computer Science, vol 13948. Springer, Cham. https://doi.org/10.1007/978-3-031-32041-5_1

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  • DOI: https://doi.org/10.1007/978-3-031-32041-5_1

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  • Print ISBN: 978-3-031-32040-8

  • Online ISBN: 978-3-031-32041-5

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