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Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components

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Book cover Models, Methods, and Tools for Complex Chip Design

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 265))

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Abstract

As the complexity of nanoscale-CMOS analog/mixed-signal (AMS) circuits and systems grows, the challenges of their design becomes exponentially more difficult. Performing accurate design simulations that entail exhaustive design space exploration has become infeasible with the increasing complexity of nano-CMOS circuits and systems integration, coupled with aggressive scaling of process technologies. Transistor-level SPICE simulations with full parasitics (RCLK) of complex circuits, which provide silicon accurate results, have run times in the order of days or weeks. With ever shrinking time to market pressures, the simulation time proves to be impractical as it can lead to longer design cycle times. The simulation time factor is further aggravated by additional design and process parameters which have to be accounted for due to increased sensitivity in deeply scaled technologies. In order to mitigate this problem, this chapter presents a two-stage approach that uses layout-accurate metamodels and efficient search algorithms for fast mixed-signal circuit and system optimization. The different components of a Phase-Locked Loop (PLL) are considered as a case study. First, the metamodel creation process is presented. A simulated annealing based optimization algorithm is then discussed for power optimization of the PLL components. It is shown that the metamodel approach speeds up the optimization phase by 2,000× with very good accuracy. The power consumption of the circuit is decreased by 22% for the baseline design and is within 8% of the circuit netlist-based, but computationally expensive approach.

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References

  1. Agarwal, A., Vemuri, R.: Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. In: IEEE/ACM International Conference on Computer-Aided Design, San Jose, pp. 430–436 (2005)

    Google Scholar 

  2. Agarwal, A., Vemuri, R.: Layout-aware RF circuit synthesis driven by worst case parasitic corners. In: 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, San Jose (2005)

    Google Scholar 

  3. Agarwal, A., Wolfe, G., Vemuri, R.: Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI, Chicago, pp. 482–487 (2005)

    Google Scholar 

  4. Basu, S., Kommineni, B., Vemuri, R.: Variation-aware macromodeling and synthesis of analog circuits using spline center and range method and dynamically reduced design space. In: 22nd International Conference on VLSI Design, New Delhi, pp. 433–438 (2009)

    Google Scholar 

  5. Bertsimas, D., Tsitsiklis, J.: Simulated annealing. Stat. Sci. 8(1), 10–15 (1993)

    Article  Google Scholar 

  6. Ding, M., Vemuri, R.: Efficient analog performance macromodeling via sequential design space decomposition. In: 19th International Conference on VLSI Design, Hyderabad, p. 4. (2006)

    Google Scholar 

  7. Doboli, A., Vemuri, R.: Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), 1556–1568 (2003)

    Article  Google Scholar 

  8. Dong, W., Feng, Z., Li, P.: Efficient VCO phase macromodel generation considering statistical parametric variations. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, pp. 874–878 (2007)

    Google Scholar 

  9. Fan, K.T., Li, R., Sudjianto, A.: Design and Modeling for Computer Experiments. Chapman and Hall/CRC, Boca Raton (2006)

    Google Scholar 

  10. Gardner, F.: Charge-pump phase-lock loops. IEEE Trans. Commun. 28(11), 1849–1858 (1980). [legacy, pre-1988]

    Google Scholar 

  11. Garitselov, O., Mohanty, S.P., Kougianos, E.: A comparative study of metamodels for fast and accurate simulation of nano-CMOS circuits. IEEE Trans. Semicond. Manuf. 25(1), 26–36 (2012)

    Article  Google Scholar 

  12. Garitselov, O., Mohanty, S.P., Kougianos, E.: Accurate polynomial metamodeling-based ultra-fast bee colony optimization of a nano-CMOS phase-locked loop. J. Low Power Electron. 8(3), 317–328 (2012)

    Article  Google Scholar 

  13. Ghai, D., Mohanty, S.P., Kougianos, E.: Design of parasitic and process-variation aware nano-CMOS RF circuits: a VCO case study. IEEE Trans. VLSI Syst. 17(9), 1339–1342 (2009)

    Article  Google Scholar 

  14. Hendrickx, W., Gorissen, D., Dhaene, T.: Grid enabled sequential design and adaptive metamodeling. In: Proceedings of the Winter Simulation Conference, Monterey, pp. 872–881 (2006)

    Google Scholar 

  15. Jin, R., Chen, W., Simpson, T.W.: Comparative studies of metamodelling techniques under multiple modelling criteria. Struct. Multidiscip. Optim. 23, 1–13 (2001)

    Article  Google Scholar 

  16. Lamecki, A., Balewski, L., Mrozowski, M.: Towards automated full-wave design of microwave circuits. In: 17th International Conference on Microwaves, Radar and Wireless Communications, Wroclaw, pp. 1–2 (2008)

    Google Scholar 

  17. Lesh, F.H.: Multi-dimensional least-squares polynomial curve fitting. Commun. ACM 2, 29–30 (1959)

    Article  MATH  Google Scholar 

  18. Mathaikutty, D.A., Shukla, S.: Metamodeling driven IP reuse for system-on-chip integration and microprocessor design. Artech House, Norwood, MA 02062 USA (2007)

    Google Scholar 

  19. McConaghy, T., Gielen, G.: Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. In: Proceedings of the IEEE International Symposium on Circuits and Systems, (ISCAS), Iasi, vol. 2, pp. 1298–1301 (2005)

    Google Scholar 

  20. McCray, A.T., McNames, J., Abercrombie, D.: Stepwise regression for identifying sources of variation in a semiconductor manufacturing process. In: IEEE Conference and Workshop on Advanced Semiconductor Manufacturing, Boston, pp. 448–452 (2004)

    Google Scholar 

  21. Mohanty, S.P., Kougianos, E., Garitselov, O., Molina, J.M.: Polynomial-metamodel assisted fast power optimization of nano-CMOS PLL components. In: Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, pp. 233–238 (2012)

    Google Scholar 

  22. Mohanty, S.P., Kougianos, E., Okobiah, O.: Optimal design of a dual-oxide nano-CMOS universal level converter for multi-v dd socs. Analog Integr. Circuits Signal Process. 72(2), 451–467 (2012)

    Article  Google Scholar 

  23. Park, J., Choi, K., Allstot, D.J.: Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier. In: Proceedings of the 8th Asia South Pacific Design Automation Conference, Kitakyushu, pp. 904–907 (2003)

    Google Scholar 

  24. Pradhan, A., Vemuri, R.: A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI, Orlando, pp. 159–162 (2008)

    Google Scholar 

  25. Pradhan, A., Vemuri, R.: Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits. In: Proceedings of the 22nd International Conference on VLSI Design, New Delhi, pp. 131–136 (2009)

    Google Scholar 

  26. Roy, S., Chen, C.C.P.: Smartsmooth: a linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. In: Asia and South Pacific Design Automation Conference, Yokohama, pp. 559–564 (2007)

    Google Scholar 

  27. Roy, S., Chen, W., Chung-Ping Chen, C., Hu, Y.H.: Numerically convex forms and their application in gate sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), 1637–1647 (2007)

    Article  Google Scholar 

  28. Samanta, R., Hu, J., Li, P.: Discrete buffer and wire sizing for link-based non-tree clock networks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(7), 1025–1035 (2010)

    Google Scholar 

  29. Tang, B.: Orthogonal array-based latin hypercubes. J. Am. Stat. Assoc. 88(424), 1392–1397 (1993)

    Article  MATH  Google Scholar 

  30. Wolfe, G., Vemuri, R.: Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2), 198–212 (2003)

    Article  Google Scholar 

  31. Wong, J.L., Davoodi, A., Khanderwal, A., Srivastava, A., Potkonjak, M.: A statistical methodology for wire-length prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), 1327–1336 (2006)

    Article  Google Scholar 

  32. Yelten, M.B., Zhu, T., Koziel, S., Franzon, P.D., Steer, M.: Demystifying surrogate modeling for circuits and systems. IEEE Circuits Syst. Mag. 12(1), 45–63 (2012)

    Article  Google Scholar 

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Acknowledgements

The chapter is based on the following presentation [21]. The authors would like to acknowledge the help of UNT graduate Dr. Oleg Garitselov and Mr. J. M. Molina who presented the conference version. The authors would like to thank the Editors of this book and FDL 2012 [21] organizers.

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Authors and Affiliations

  1. Computer Science and Engineering, University of North Texas, Denton, TX, 76203, USA

    Saraju P. Mohanty

  2. Engineering Technology, University of North Texas, Denton, TX, 76203, USA

    Elias Kougianos

Authors
  1. Saraju P. Mohanty
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  2. Elias Kougianos
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Correspondence to Saraju P. Mohanty .

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Editors and Affiliations

  1. Institute of Computer Technology, Vienna University of Technology, Vienna, Austria

    Jan Haase

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Mohanty, S.P., Kougianos, E. (2014). Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components. In: Haase, J. (eds) Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering, vol 265. Springer, Cham. https://doi.org/10.1007/978-3-319-01418-0_11

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  • DOI: https://doi.org/10.1007/978-3-319-01418-0_11

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-01417-3

  • Online ISBN: 978-3-319-01418-0

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