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SCandal: SystemC Analysis for Nondeterminism Anomalies

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 265))

Abstract

SystemC is the de facto standard language for electronic system level design and simulation. SystemC simulations may contain nondeterminism caused by dependencies on the process execution order (PEO) due to data dependencies of SystemC logical processes (LP) within delta-cycles. In practice, often this is not an issue, since simulation execution appears to be deterministic due to deterministic SystemC scheduler implementations.However, to satisfy the increasing need for simulation speed, parallel SystemC engines are being researched: With no fixed strict total order among LPs executed in parallel, nondeterministic behavior is more likely to surface and more difficult to debug, threatening the viability to use simulation for debugging use-cases.This work presents a new method to test for nondeterminism: Anomalies are detected by running a simulation twice in sequential simulation mode while systematically varying the PEO, and without the need for source code analysis. Feasibility is demonstrated with several case studies.

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Acknowledgements

This work has been supported by the German excellence cluster UMIC and the European FP7 project EURETILE.

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Correspondence to Jan Henrik Weinstock .

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Weinstock, J.H., Schumacher, C., Leupers, R., Ascheid, G. (2014). SCandal: SystemC Analysis for Nondeterminism Anomalies. In: Haase, J. (eds) Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering, vol 265. Springer, Cham. https://doi.org/10.1007/978-3-319-01418-0_5

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  • DOI: https://doi.org/10.1007/978-3-319-01418-0_5

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