Abstract
Post-silicon functional validation poses unique challenges that must be overcome by bring-up tools. One such major challenge is the requirement to reduce overhead associated with the testing procedures, thereby ensuring that the expensive silicon platform is utilized to its utmost extent. Another crucial requirement is to conduct high-quality validation that guarantees the design is bug-free prior to its shipment to customers. Our work addresses these issues in the realm of software-based self-tests.
We propose a novel solution that satisfies these two requirements. The solution calls for shifting the preparation of complex data from the runtime to the offline phase that takes place before the software test is compiled and loaded onto the silicon platform. This data is then variably used by the test-case to ensure high testing quality while retaining silicon utilization.
We demonstrate the applicability of our method in the context of baremetal functional exercisers. An exerciser is a unique type of self-test that, once loaded onto the system, continuously generates test-cases, executes them, and checks their results. To ensure high silicon utilization, the exerciser’s software must be kept lightweight and simple. This requirement contradicts the demand for high-quality validation, as the latter calls for complex test generation, which in turn implies extensive, complex computation. Our solution bridges these contradicting requirements.
We implemented our proposed solution scheme in IBM’s Threadmill post-silicon exerciser, and we demonstrate the value of this scheme in two highly important domains: address translation path generation and memory access management.
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References
Abramovici, M., Bradley, P., Dwarakanath, K.N., Levin, P., Memmi, G., Miller, D.: A reconfigurable design-for-debug infrastructure for SoCs. In: DAC, pp. 7–12 (2006)
Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., Ziv, A.: Genesys-pro: Innovations in test program generation for functional processor verification. IEEE Design & Test of Computers 21(2), 84–93 (2004)
Adir, A., Copty, S., Landa, S., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J.: A unified methodology for pre-silicon verification and post-silicon validation. In: DATE, pp. 1590–1595 (2011)
Adir, A., Emek, R., Katz, Y., Koyfman, A.: Deeptrans - a model-based approach to functional verification of address translation mechanisms. In: MTV, pp. 3–6 (2003)
Adir, A., Golubev, M., Landa, S., Nahir, A., Shurek, G., Sokhin, V., Ziv, A.: Threadmill: a post-silicon exerciser for multi-threaded processors. In: DAC, pp. 860–865 (2011)
Adir, A., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J.: Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor. In: DAC, pp. 569–574 (2011)
Adir, A., Nahir, A., Ziv, A.: Concurrent generation of concurrent programs for post-silicon validation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8), 1297–1302 (2012)
Adir, A., Nahir, A., Ziv, A., Meissner, C., Schumann, J.: Reaching coverage closure in post-silicon validation. In: Raz, O. (ed.) HVC 2010. LNCS, vol. 6504, pp. 60–75. Springer, Heidelberg (2010)
Adve, S.V., Hill, M.D.: A unified formalization of four shared-memory models. IEEE Trans. Parallel Distrib. Syst. 4(6), 613–624 (1993)
Alglave, J., Maranget, L., Sarkar, S., Sewell, P.: litmus: Running tests against hardware. In: Abdulla, P.A., Leino, K.R.M. (eds.) TACAS 2011. LNCS, vol. 6605, pp. 41–44. Springer, Heidelberg (2011)
Bin, E., Emek, R., Shurek, G., Ziv, A.: Using a constraint satisfaction formulation and solution techniques for random test program generation. IBM Systems Jouranl 41(3), 386–402 (2002)
Chen, K., Malik, S., Patra, P.: Runtime validation of memory ordering using constraint graph checking. In: HPCA, pp. 415–426 (2008)
De Paula, F.M., Gort, M., Hu, A.J., Wilton, S.J.E., Yang, J.: Backspace: formal analysis for post-silicon debug. In: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, pp. 1–10 (November 2008)
Deorio, A., Li, J., Bertacco, V.: Bridging pre- and post-silicon debugging with BiPeD. In: ICCAD (November 2012) (to appear)
Emek, R., Jaeger, I., Naveh, Y., Bergman, G., Aloni, G., Katz, Y., Farkash, M., Dozoretz, I., Goldin, A.: X-gen: a random test-case generator for systems and socs. In: HLDVT, pp. 145–150 (2002)
Gharachorloo, K., Lenoski, D., Laudon, J., Gibbons, P.B., Gupta, A., Hennessy, J.L.: Memory consistency and event ordering in scalable shared-memory multiprocessors. In: 25 Years ISCA: Retrospectives and Reprints, pp. 376–387 (1998)
Gray, R.: Post-silicon validation experience: History, trends, and challenges. In: GSRC Workshop on Post-Si Validation (June 2008)
Hong, T., Li, Y., Park, S.-B., Mui, D., Lin, D., Kaleq, Z.A., Hakim, N., Naeimi, H., Gardner, D.S., Mitra, S.: QED: Quick error detection tests for effective post-silicon validation. In: ITC, pp. 154–163 (2010)
Keshava, J., Hakim, N., Prudvi, C.: Post-silicon validation challenges: how EDA and academia can help. In: DAC 2010, pp. 3–7. ACM (2010)
Lin, D., Hong, T., Fallah, F., Hakim, N., Mitra, S.: Quick detection of difficult bugs for effective post-silicon validation. In: DAC, pp. 561–566 (2012)
Mitra, S., Lin, D., Hakim, N., Gardner, D.S.: Bug localization techniques for effective post-silicon validation. In: ASP-DAC, p. 291 (2012)
Mitra, S., Seshia, S.A., Nicolici, N.: Post-silicon validation opportunities, challenges and recent advances. In: DAC, pp. 12–17 (2010)
Nahir, A., Ziv, A., Galivanche, R., Hu, A.J., Abramovici, M., Camilleri, A., Bentley, B., Foster, H., Bertacco, V., Kapoor, S.: Bridging pre-silicon verification and post-silicon validation. In: DAC, pp. 94–95 (2010)
Nahir, A., Ziv, A., Panda, S.: Optimizing test-generation to the execution platform. In: ASP-DAC, pp. 304–309 (2012)
Patra, P.: On the cusp of a validation wall. IEEE Design and Test of Computers 24, 193–196 (2007)
Psarakis, M., Gizopoulos, D., Sánchez, E.E., Reorda, M.S.: Microprocessor software-based self-testing. IEEE Design & Test of Computers 27(3), 4–19 (2010)
Rotithor, H.G.: Postsilicon validation methodology for microprocessors. IEEE Design & Test of Computers 17(4), 77–88 (2000)
Singerman, E., Abarbanel, Y., Baartmans, S.: Transaction based pre-to-post silicon validation. In: DAC, pp. 564–568 (2011)
Storm, J.: Random test generators for microprocessor design validation (2006), http://www.oracle.com/technetwork/systems/opensparc/53-rand-test-gen-validation-1530392.pdf (accessed January 9, 2013)
Theodorou, G., Chatzopoulos, S., Kranitis, N., Paschalis, A.M., Gizopoulos, D.: A software-based self-test methodology for on-line testing of data tlbs. In: European Test Symposium (2012)
Theodorou, G., Kranitis, N., Paschalis, A.M., Gizopoulos, D.: Software-based self test methodology for on-line testing of l1 caches in multithreaded multicore architectures. IEEE Trans. VLSI Syst. 21(4), 786–790 (2013)
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Kadry, W., Koyfman, A., Krestyashyn, D., Landa, S., Nahir, A., Sokhin, V. (2013). Improving Post-silicon Validation Efficiency by Using Pre-generated Data. In: Bertacco, V., Legay, A. (eds) Hardware and Software: Verification and Testing. HVC 2013. Lecture Notes in Computer Science, vol 8244. Springer, Cham. https://doi.org/10.1007/978-3-319-03077-7_12
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DOI: https://doi.org/10.1007/978-3-319-03077-7_12
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