Abstract
Tools and services are available that modify the hardware description, compilers, and tools to build application specific instruction-set architectures (ASIPs).
This work introduces an automatic approach in identifying ”hot” code idioms: find and count recurring tuples of assembly instructions (N-grams) in a simulator trace. Our analysis gives a short list of frequent combinations of instructions, even across control-flow boundaries. These candidates are most promising to optimize.
On the example of an implementation of the Smith-Waterman-Algorithm for String-Alignment in C, running on a PD_RISC by Synopsys Processor Designer, the hot part of the assembly code is identified and manually replaced by an intrinsic function of the same behavior. Results include the growth in logic of the processor, speed-up of the program, and reduction in energy consumption, due to the first round of applying the proposed technique.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bala, V., Duesterwald, E., Banerjia, S.: Dynamo: A Transparent Dynamic Optimization System. ACM SIGPLAN Notices 35(5), 1–12 (2000), http://portal.acm.org/citation.cfm?doid=358438.349303 , http://dl.acm.org/citation.cfm?id=358438.349303
Bansal, S.: Peephole Superoptimization. ProQuest (2008), http://books.google.com/books?id=DITv8TZSBbEC&pgis=1
Barat, F., Lauwereins, R.: Reconfigurable Instruction Set Processors: A Survey, p. 168 (June 2000), http://dl.acm.org/citation.cfm?id=827261.828228
Bispo, J., Paulino, N., Cardoso, J.M.P., Ferreira, J.C.: Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Transactions on Industrial Informatics 9(3), 1625–1634 (2013), http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6392266
Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., Flautner, K.: An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. ACM SIGARCH Computer Architecture News 33(2), 272–283 (2005), http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=1431563 , http://dl.acm.org/citation.cfm?id=1080695.1069993 , http://portal.acm.org/citation.cfm?doid=1080695.1069993 , http://dx.doi.org/10.1109/ISCA.2005.9
Dutt, N.D., Lee, J.E., Choi, K.: Energy-efficient instruction set synthesis for application-specific processors. In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003, pp. 330–333. ACM (2003), http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1231889 , http://home.unist.ac.kr/professor/jlee/public/papers/03islped-isa-energy.pdf
Galuzzi, C., Bertels, K.: The instruction-set extension problem: A survey. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds.) ARC 2008. LNCS, vol. 4943, pp. 209–220. Springer, Heidelberg (2008), http://link.springer.com/chapter/10.1007/978-3-540-78610-8_21
Grad, M., Plessl, C.: On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors. International Journal of Reconfigurable Computing 2012, 1–21 (2012), http://dl.acm.org/citation.cfm?id=2213807.2213808
Hoffmann, A., Meyr, H., Leupers, R.: Architecture Exploration for Embedded Processors with LISA. Springer US, Boston (2002), http://link.springer.com/10.1007/978-1-4757-4538-2
McFarling, S., Hennesey, J.: Reducing the cost of branches. ACM SIGARCH Computer Architecture News 14(2), 396–403 (1986), http://dl.acm.org/citation.cfm?id=17407.17402
McKeeman, W.M.: Peephole optimization. Communications of the ACM 8(7), 443–444 (1965), http://dl.acm.org/citation.cfm?id=364995.365000
Med, M., Krall, A.: Instruction Set Encoding Optimization for Code Size Reduction. In: 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 9–17. IEEE (July 2007), http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4285728 , http://www.cse.unt.edu/~sweany/CSCE6650/HANDOUTS/29.pdf
Tanenbaum, A.S., van Staveren, H., Stevenson, J.W.: Using Peephole Optimization on Intermediate Code. ACM Transactions on Programming Languages and Systems 4(1), 21–36 (1982), http://dl.acm.org/citation.cfm?id=357153.357155
Vahid, F., Stitt, G., Lysecky, R.: Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer 41(7), 40–46 (2008), http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=4563878 , http://www.inf.pucrs.br/~moraes/prototip/artigos/warp_processing.pdf
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this paper
Cite this paper
Ferger, M., Hübner, M. (2014). Instruction Set Optimization for Application Specific Processors. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_28
Download citation
DOI: https://doi.org/10.1007/978-3-319-05960-0_28
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-05959-4
Online ISBN: 978-3-319-05960-0
eBook Packages: Computer ScienceComputer Science (R0)