Abstract
Run-time reconfiguration provides an opportunity to increase performance, reduce cost and improve energy efficiency in FPGA-based systems. However, run-time reconfigurable systems are more complex to implement than static only systems. This increases time to market, and introduces run-time overhead into the system. Our research aims to raise the abstraction level to develop run-time reconfigurable systems. We present operating system extensions which enable seamless integration of run-time reconfigurable hardware threads into applications. To improve resource utilization, the hardware threads are placed on a fine granularity tile grid. We take advantage of a relocatable module placer targeting modern FPGA to manage the reconfigurable area. The module placer accurately models the FPGA resources to compute feasible placement locations for the hardware threads at run-time. Finally, we evaluate our work by means of a case study that consists of a synthetic application to validate the functionality and performance of the implementation. The results show a reduction in reconfiguration time of up to 42% and more than double resource utilization.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Sohanghpurwala, A.A., Athanas, P., Frangieh, T., Wood, A.: OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Number Xdl, pp. 228–235. IEEE (May 2011)
Beckhoff, C., Koch, D., Torresen, J.: Go Ahead: A Partial Reconfiguration Framework. In: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 37–44. IEEE (April 2012)
Jara-Berrocal, A., Gordon-Ross, A.: An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips. In: ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 219–222. IEEE (September 2011)
Wang, Y., Zhou, X., Wang, L., Yan, J., Luk, W.: SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (99), 1–14 (2013)
Lubbers, E., Platzner, M.: ReconOS: An RTOS Supporting Hard-and Software Threads. In: 2007 International Conference on Field Programmable Logic and Applications, pp. 441–446. IEEE (August 2007)
Wold, A., Koch, D., Torresen, J.: Enhancing Resource Utilization with Design Alternatives in Runtime Reconfigurable Systems. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Anchorage, pp. 264–270. IEEE (May 2011)
Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., Ruckert, U.: Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(6), 1048–1061 (2011)
Koch, D., Beckhoff, C., Torresen, J.: Zero logic overhead integration of partially reconfigurable modules. In: Proceedings of the 23rd Symposium on Integrated Circuits and System Design - SBCCI 2010, p. 103. ACM Press, New York (2010)
COSRECOS: Context switching reconfigurable hardware for communication systems (cosrecos), http://www.mn.uio.no/ifi/english/research/projects/cosrecos .
EPiCS: Engineering proprioception in computing systems (epics), http://www.epics-project.eu
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this paper
Cite this paper
Wold, A., Agne, A., Torresen, J. (2014). Relocatable Hardware Threads in Run-Time Reconfigurable Systems. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-05960-0_6
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-05959-4
Online ISBN: 978-3-319-05960-0
eBook Packages: Computer ScienceComputer Science (R0)