Abstract
The rediscovery of VLIW architecture in the field of embedded multimedia applications introduces new challenges for computing paradigms historically oriented towards Instruction Level Parallelisms and performance optimization. In this work we perform an extensive multi-objective analysis which includes VLIW compiler as part of the configuration space, avoiding any explicit distinction between micro-architectural parameters and compilation strategies. After performing an high-level estimation of power/performance trade-offs by compiling and simulating some common application kernels, we qualitatively and quantitatively analyze of how the design space available can be greatly affected by the interaction of compiler behavior, processor-related features and memory subsystem.
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Patti, D., Palesi, M., Catania, V. (2014). Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. In: Silhavy, R., Senkerik, R., Oplatkova, Z., Silhavy, P., Prokopova, Z. (eds) Modern Trends and Techniques in Computer Science. Advances in Intelligent Systems and Computing, vol 285. Springer, Cham. https://doi.org/10.1007/978-3-319-06740-7_18
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DOI: https://doi.org/10.1007/978-3-319-06740-7_18
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