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Compile Time Modeling of Off-Chip Memory Bandwidth for Parallel Loops

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Languages and Compilers for Parallel Computing (LCPC 2013)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 8664))

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Abstract

In this paper, we present a statistical model to predict the off-chip memory bandwidth required by a parallel loop during its execution. It is a compile-time modeling technique that derives the correlations between memory bandwidth requirement and data access patterns of multithreaded applications. This model could be used by the compiler and performance tools to predict when the sustainable memory bandwidth of the system will be reached by the application during execution, and to determine an optimal number of threads that should be configured to execute a specific parallel loop according to its memory reference patterns. Awareness of the performance impact of oversubscribed memory bandwidth can also help programmers to take into account the additional latency caused by the contention, and to minimize the overhead by tuning the memory access behavior of applications. We evaluated this model in terms of both technical accuracy and prediction accuracy by comparing the modeling results with the measured results. The evaluation demonstrates its accuracy in both system bandwidth modeling and application bandwidth modeling.

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Acknowledgement

This work was supported in part by the National Science Foundations Computer Systems Research program under Award No. CCF-0833201 and Department of Energy under Award Agreement No. DE-FC02-12ER26099. The evaluation platform used for this work was supported by the National Science Foundation’s Computer Systems Research program under Award No. CNS-0833201 and CRI-0958464.

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Authors and Affiliations

  1. Computer Science Department, University of Houston, Houston, Texas, USA

    Munara Tolubaeva, Yonghong Yan & Barbara Chapman

Authors
  1. Munara Tolubaeva
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  2. Yonghong Yan
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  3. Barbara Chapman
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Corresponding author

Correspondence to Munara Tolubaeva .

Editor information

Editors and Affiliations

  1. Silicon Valley, Qualcomm Research, San Jose, California, USA

    Călin Cașcaval

  2. Silicon Valley, Qualcomm Research, San Jose, California, USA

    Pablo Montesinos

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Tolubaeva, M., Yan, Y., Chapman, B. (2014). Compile Time Modeling of Off-Chip Memory Bandwidth for Parallel Loops. In: Cașcaval, C., Montesinos, P. (eds) Languages and Compilers for Parallel Computing. LCPC 2013. Lecture Notes in Computer Science(), vol 8664. Springer, Cham. https://doi.org/10.1007/978-3-319-09967-5_17

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  • DOI: https://doi.org/10.1007/978-3-319-09967-5_17

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-09966-8

  • Online ISBN: 978-3-319-09967-5

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